OK, lets reduce ramping fabs, eliminate D1B (same as F20), eliminate all the flash fabs and eliminate development fabs. What is left:
D1C - (eliminated)
D1D - 175,000 sq. ft. [development], eliminated (we won't count AMD's development fab either)
D2 - 36,000 sq. ft. in 1991 [.18/.13] flash
RP1 - 56,000 sq. ft. [development], eliminated
FAB1-7 - 435,000 sq. ft. (flash, eliminated)
FAB8 - 0.35u obsolete, eliminated
FAB9 - 120,000 flash, eliminated
FAB10 - 100,000 sq. ft.? [.25/.18], reduce to 80,000
FAB11 - 120,000 sq. ft.? [.18 -> .13] flash, eliminated
FAB11x - 135,000 sq. ft. [.13]
FAB12 - 135,000 sq. ft. [.18]
FAB14 - 90,000 sq. ft. [.25/.18]
FAB15 - 120,000? [.35/25] -> [.18/.13] flash, eliminated
FAB16 - On Hold, eliminated
FAB17 - 95,000 sq. ft. [.13]
FAB18 - 80,000 sq. ft. [.18]
FAB20/D1BR - 200,000 [.13], reduce to 100,000 for ramping
FAB23 - 120,000 sq. ft. [.18] flash, eliminated
FAB22 - 133,000 sq. ft. [.13], reduce to 100,000 for ramping
FAB24 - 135,000 sq. ft. - under construction, eliminated
What is left is now
FAB10 - 80,000 sq. ft.(reduced for ?) [.25/.18]
FAB11x - 135,000 sq. ft. [.13]
FAB12 - 135,000 sq. ft. [.18]
FAB14 - 90,000 sq. ft. [.25/.18]
FAB17 - 95,000 sq. ft. [.13]
FAB18 - 80,000 sq. ft. [.18]
FAB20/D1BR - 100,000 sq. ft. (reduced) [.13]
FAB22 - 100,000 sq. ft. (reduced) [.13]
We are left with 815,000 sf of clean room space. Eliminating the huge D1D (175,000 s.f.) is probably going too far -- a fab this size is obviously being used for production as well as development.
Anyway, I'll further reduce the total by 10% to account for chipsets for 35% of the CPU's sold which have a die size averaging less than 1/3 the size of the CPU's. (I use 35% rather than 50% because Intel doesn't make them all.)
I'll reduce it 5% for Intel's COMM and OTHER categories excluding flash, which only provide 15% of revenues. Most of these are made in the obsolete fabs or flash fabs and many non-CPU products are not chips (motherboards, for example). (We'll eliminate AMD's non-CPU capacity as well.)
815,000 x 0.85 = 692,750 useable Intel (CPU) clean room space
Intel doesn't need to use any of this space to experiment on 0.09 or other process variations. They have two huge development fabs to do that, much larger than AMD's development fab.
Now, AMD's capacity consists of
Fab30 115,000 sf at ~70% of capacity last quarter = 80,500
Fab25 120,000 sf x 0.5 for flash = 60,000
TOTAL USEABLE AMD CLEAN ROOM (CPU) SPACE = 140,500 s.f.
AMD sold 8M CPU's, so they produced 56.9 CPU's per s.f.
INTEL sold 32M CPU's, or 46.2 CPU's per s.f.
Given that Intel's average die size is about 1/3 bigger than AMD's, the numbers become
AMD: 56.9 AMD-sized CPU's per s.f.
INTEL: 61.6 AMD-sized CPU's per s.f.
But we need one further adjustment; Intel is already using 12" wafers. Even if only 10% of Intel's square footage is using 12" wafers, that would increase their effective square footage by 10%, since CPU's per wafer should double (at least!). Using an adjusted square footage of 762,000 for Intel (+10%), the numbers are
AMD: 56.9 AMD-sized CPU's per s.f.
INTEL: 56 AMD-sized CPU's per s.f.
One could also question why AMD was not at full capacity in Fab30. The only reasonable explanation is that part of the capacity is being converted to 0.13u, and that part of the fab did not consume many wafers or produce many CPU's.
Obviously, Intel and AMD have very similar yields. For Intel to claim they have 50% higher yields is patently absurd. The fact that Intel gets similar yields with larger die sizes means they have better defect density, but that is not the meaning of the word, "yield."
Regarding your specific points:
D1B and F20 are the same
True or not, I combined them
many of the new fabs (D1C, F11X, F22, F17) haven't ramped yet
D1C not on my list, F22 reduced by 25%, F11X and F17 weren't reduced, but megafab F20 was reduced by 50%.
Petz |
