Dan3, Thanks for the links.
eet.com
TSMC's Sheng put the bottom line succinctly: "For an average fabless semiconductor customer using our 300-mm line, a wafer lot is anywhere from three to seven wafers."
Seems there's not a lot of wafers in a wafer lot these days.
Our whole approach was based on the assumption-true so far-that chip failures were dominated by defects," Billat explained. "But now it is fabrication that dominates yield, not defect density. This will require us to forge a link between design and test.
Somebody should be telling Yousef about this concept -- but I'm not the one.
eetimes.com
Buss said CMOS scaling will continue to offer performance, density and cost advantages for the next decade, but that CMOS will run out of steam by 2012 when gate lengths are at 10 nanometers, or 0.01 microns. "By CMOS, I include all of the double-gate structures," he said. "My guess is that by then we will be using a dual-gate FinFET," he said.
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Also, the industry must put more funding into 3-D structures, in which logic devices, memory, sensors, and chip-to-chip optical interconnects would be stacked and connected vertically in a single package.
Looks like this guy thinks basic physics isn't going to be a problem for a while, but there will have to be some difficult process engineering and design work.
tgptndr |
