Advanced Micro Devices - Moderated (AMD) Message Board

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Technology Stocks : Advanced Micro Devices - Moderated (AMD)

AMD 213.43

+6.2%

Dec 19 9:30 AM EST

Public Reply Prvt Reply Mark as Last Read File

Previous 10 Next 10 Previous Next

To: Ali Chen who wrote (80418)	5/21/2002 3:34:50 PM
From: THE WATSONYOUTH	Read Replies (1) of 275872

The formula usually implies some lump capacitance which includes wire loads, where the gate capacitance is not the biggest part, AFAIK. Also, does not a shrink implies a sort of thinner oxides, to maintain "true" scaling? That would offset the decreasing size of gate capacitor. I believe that in general the C stays about the same. More, with deeper shrinks, the "short current" started to be of more concern, so all things become trickier. Yea....not sure what percentage is gate capacitance ....my guess is around 40%-50%. The 10% NW shrink did not include a thinning of the gate oxide. The performance benefit is small. So, overall capacitance does decrease somewhat within a process generation with constant gate oxide as the gate length is shortened. As far as I can remember. THE WATSONYOUTH

Report TOU Violation

Share This Post

Public Reply Prvt Reply Mark as Last Read File

Previous 10 Next 10 Previous Next