Advanced Micro Devices - Moderated (AMD) Message Board

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Technology Stocks : Advanced Micro Devices - Moderated (AMD)

AMD 214.18

-0.5%

Dec 31 3:59 PM EST

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To: wanna_bmw who wrote (80808)	5/28/2002 11:26:42 AM
From: Ali Chen	Read Replies (1) of 275872

"In the first situation, they are saying that an inbound memory write needs to flush those cache lines from the CPU caches, which is correct, except that they forget to mention that modified data needs to be written back" Wrong. Inbounded memory Write does not need to flash cache lines since it makes no sense in first place - the flushed data will be over-written anyway. The only thing a CPU does it marks the corresponding cache line as "invalid", so when the CPU needs the same data, the BUI will read them from memory. The cacheline flush has to be done when "other agent" READs from memory. In case when the CPU contained a newer, "modified" image of the main memory location, the memory must be updated (chache line flushed) before the READ can proceed to the requesting agent. The cache coherency protocol is one of the most important part of SMP architecture, and it is very unprofessional to mess up with bus snooping basics. Instead of expressing your own (and wrong) opinions, I strongly suggest to familiarize yourself at least with popular interpretation of SMP architecture like T.Shanley's "PentiumPro and Pentium II System Architecture", ISBN 0-201-30973-4, Addison-Wesley. - Ali

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