Here you go again. Could you ever stop and think?
"They correctly said that the cache must get invalidated or "flushed" as a result to an I/O device writing (inbound) to main memory."
Please go and learn that "invalidating" of a cacheline
has nothing to do with "flushing" of the cacheline data,
one does not imply another, and "or" is totally
inapropriate. On "other agent's" writes (the other
agent meaning either a bus-mastering I/O device, or
other CPU), the cacheline is not "flushed", it makes
no sense whatsoever since the data will be overwritten
anyway. What is so hard to understand here?
"As I tried to explain before, they miss the details that a write to a cache line that is not previously owned by the requesting device must do a read for ownership, which as you explain is the direct cause for a cache invalidate or implicit write back (flush)."
Nice try, wanna. In that particular paragraph Ace's
were talking about bustmastering I/O device, they do
not have caches and do not do write-allocate, so you
are grasping at the straw second time. But your creativity
must be commended, your grade may move from "F" to "D".
"Must do a read for ownership", wow, that was good.
"More broken English."
Ha. How typical for a loser in an
exchange, to pick up on grammar. Ok, what's next?
Putting me on ignore I guess? BHAHAHAHAHA.
"and challenge my level of experience ... Am I upsetting you?"
Not really. Actually, it gives me more confidence in AMD
as long as experts like yourself and Yousef are working
hard for Intel. Thanks.
- Ali |
