If Intel was in so in bed with the manufacturers and got the best deal on the latest MicraScans, then why did they have to use that half ass notched process (since abandoned) to achieve their .18um gate lengths.
-- SIGH..... If you recall, mid-90's was not 0.18u Technologhy, it was 0.35u. And as far as the Notched Poly, who says intel "have to use" Notched Poly to achieve 0.18u Gate lengths. 0.18u started out without Notched Poly and achieved the required Gate lengths. Notched Poly was a Process Improvement put in by The Process Engineers, not the Development Engineers. If I find something that Speeds up my chips, I use it. besides, who says it's been abandoned? How Notched Poly came to be is actually a really interesting story, but somehow, I don't think (based on your "half assed" comment) that you're really interested in an answer at all. Feel better now that you've bashed?
MicraScan 3, combined with carefully controlled RIE trim processes could easily achieve Intel's .18um minimum channel lengths (and somewhat beyond) with excellent process control. It seems that everyone except Intel knew this.
-- And that's the fly in your ointment, "Carefully Controlled". Achieving what you sugest may have been fine for your buddies at IBM and low volume, but to maintain those line widths using the techniques you suggest, was determined to be far too labor intensive, too costly, and too slow throughput for high volume manufacturing.
. I'm sure Intel will not admit it, but that notch process (even based on a few
random SEMs) was very crude.
THE WATSONYOUTH
So, I was there, you weren't. I'm not at liberty to discus any further specifics of Notched Poly. Even if some people consider it "crude", it worked. That's what obviously sticks in your craw.
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