Trouble at 130-nm node causes finger pointing
(Thanks to Survivin on the AMD thread for this. Looks like Intel is ahead of the industry on .13u manufacturing. They've had a product for almost a year now, while many others are scrambling to catch up. The question is, will they continue to have an advantage at the 90nm node?)
siliconstrategies.com
NEW ORLEANS — Design Automation Conference attendees spent their evenings chugging beer and dancing the night away like college students on spring break. To some it was respite from the rigors of booth duty and back-to-back meetings. To technologists and engineers, it was an escape from a much deeper level of pain and frustration they are feeling as denizens of an industry in crisis.
Though the EDA industry is on solid footing, its customers are still reeling from a devastating economic blow. What's worse, it's happening at a time when semiconductor companies more than ever need to spend on tools, manufacturing technologies and design teams if they are to stay relevant.
Pressures on the chip industry to restructure are well-known, but what's less talked about is the design and manufacturing morass the industry finds itself in. By most accounts, the 0.13-micron process technology node has been a major disappointment. This can be blamed partly on canceled projects and customers who no longer exist, but the other half of the problem is the seemingly intractable design and manufacturing troubles.
Despite having had more than a year to work out the glitches, the chip and EDA industries are still grappling with low yields and false wafer starts caused by poor signal integrity, botched attempts at integrating new materials and an exceedingly high degree of in-die and in-wafer slop.
At 0.13 micron, for example, there are more interactions between libraries on the same rows and those on different rows. That's one reason it's taking an unacceptably long time to reach post-tapeout fabrication, said Mark Lavin of IBM's T.J. Watson Research Center.
To Lavin, the problems go beyond the typical ones expected with any new process technology. "Every generation causes some incremental hurt. We're now at the point where we're going through a noticeable discontinuity at the 130-nanometer node," he said. "What hurts next is in fact hurting now."
Slower demand
One company feeling the pinch is Numerical Technologies Inc., which develops products to enable subwavelength technology. The company said Monday (June 10) that it expected 2002 revenue to be $46 million, or $14 million less than anticipated. Numerical's stock closed at $3.43 on Friday, against the $39 per share it commanded earlier this year.
The company blamed chip makers' reluctance to ramp up 0.13-micron designs. "There is a delay in the number of cell libraries being built for the process," said Susan Lippincott, director of corporate marketing at Numerical. "It's not that there isn't any demand, but the 0.13-micron demand is slower."
Numerical's troubles provide more evidence that, unlike previous downturns, design activity did not continue unabated during this slowdown. Starts of both cell-based ASICs and PLD-based projects fell about 3 percent last year and are unlikely to see much pickup this year, sources said. Gate array designs fell even more rapidly, said Bryan Lewis, chief analyst at Gartner Dataquest. "Instead of continuing design activity, system OEMs delayed or canceled projects," he said.
Indeed, some in the industry are questioning aspects of the evolution of chip technology that would have once been taken for granted. At one DAC session here, attendees were asked whether a 10 million-gate ASIC is feasible. Three engineers that had recently managed designs of that size answered yes, but only after making some serious qualifications.
Chris Malachowski, vice president of engineering at Nvidia Corp., described a rigorous but relatively conventional design flow for the 63 million-transistor GeForce 4 graphics chip, which is based on 0.15-micron design rules. The project started with intensive modeling of the design in C. The C code was then used as a reference model while the design was recoded in Verilog.
Malachowski said that first silicon had 19 reported functional problems, only seven of which required repair. All seven were corrected in the metal, allowing the team to meet its target of approximately nine months to tapeout and 100 days between tapeout and production ramp.
Takes experience, luck
Malachowski said the design team's experience was key to solving the problems, yet he wondered whether the team was really good or just lucky. "It's hard to judge when you are through with verification," he said. "Even with great stuck-at coverage, the only proof is that the chip works in applications. And it's not the logic errors. . . . Noise problems can be a lot worse to fix."
Aurangzeb Khan, group general manager at Simplex Solutions Inc., described analysis techniques — including advanced interconnect modeling and a design flow based on physical resynthesis, detailed IR-drop analysis and crosstalk prevention — that have produced 23 tapeouts for the physical-design service, all successful at first silicon.
But in a cautionary postscript, Khan detailed how Simplex builds techniques upon research, then constructs methodology on techniques and finally builds commercial tools from maturing methodology, again emphasizing the irreplaceable role that experience plays in success.
Christian Berthet of STMicroelectronics, who described development of a GPRS feature-phone chip, said the design hinged on reuse of existing cores, including an ST120 DSP core and an ARM core. Yet it still required 100,000 lines of C verification code, two ASIC emulation environments — one from Aptix Corp. and one custom-FPGA-based — and five man-years just to create the verification code. Berthet said the job drew on ST's experience at every level, from requirements definition to test design.
All three companies had to marshal large design teams — typically, 40 to 70 engineers in implementation alone — and a good deal of capital. Malachowski estimated that Nvidia spent $160 million on tools and $40 million just on emulation systems for the GeForce 4 project. Khan said Simplex physical-design services for a chip of this size would run between $2 million and $5 million in nonrecurring expenses by tapeout. Thus, front-end investment is so staggering that only the most well-funded players can consider it.
Some designers, meanwhile, voiced their frustration over bottlenecks in design flows and pointed a finger at EDA vendors. The design flows are broken, said users like John Szetela, manager for tools integration at Advanced Micro Devices Inc., and Hilton Kirk, manager of physical design at Philips Research Labs. "Late changes in the design flow are inevitable — and the automated design flow is too slow to accommodate them," said Szetela. Point tools for analyzing postlayout parasitics — IR drop, electromigration, antenna effects, signal integrity — conflict with timing-analysis tools, he said.
"The tool flow is not straightforward; there are lots of little tools," conceded Patrick Groeneveld of Magma Design Automation Inc. "Even if the user is the bottleneck, the tools should [be] better. Analog design is always manual; the rest needs to be brutally automatic."
Tighter tool integration supported by a universal database was high on the wish list of panelists. Philips' Kirk, for example, urged support of Cadence Design Systems Inc.'s OpenAccess interoperability initiative.
EDA vendors have always been an easy target, but there are some issues that the chip industry as a whole just can't seem to get right. The young intellectual-property exchange business, for example, still has a way to go if vendors are to start trading commercial analog IP, many said.
Commercial IP must be reusable and retargetable, said Roy McGuffin, president and chief executive officer of Antrim Design Systems Inc. "Typically that's been achieved for digital, but in analog, it's never been achieved."
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