Advanced Micro Devices - Moderated (AMD) Message Board

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Technology Stocks : Advanced Micro Devices - Moderated (AMD)

AMD 207.91

+0.2%

2:11 PM EST

Public Reply Prvt Reply Mark as Last Read File

Previous 10 Next 10 Previous Next

To: wanna_bmw who wrote (82747)	6/18/2002 8:37:39 AM
From: Dan3	Read Replies (1) of 275872

Re: you shouldn't assume that a Xeon would scale 100% from 2-way to 4-way Scaling the number of processors doesn't enter in to it. 700mhz PIII with 2 meg cache had the identical score to 800mhz Itanium with 4 meg cache. And, a quick review of the test results seems to indicate that cache size is important for SAP - Itanium-Too-Late will have smaller caches (though they'll be on-die, which is probably the source of most of that claimed performance increase). On cache hungry applications like SAP, a big off die cache can be better than a small, on die cache. Itanium-Too-Late many not do much better on these sorts of enterprise applications than Itanic-Already-On-The-Bottom. Have you seen the latest news that Intel is having to ship Itanic-Too-Late as pre-built boxes? The OEMs aren't willing to spend any of their own money on Itanic-Anything development. What's that tell you?

Report TOU Violation

Share This Post

Public Reply Prvt Reply Mark as Last Read File

Previous 10 Next 10 Previous Next