yesterday at SEMICON West -- here's the program description for a presentation involving a senior IBIS engineer, Michael Alles. See semi.org
SEMICON West 97 Silicon-On-Insulator (SOI) Processing Technology
Monday, July 14 8:15 am - 12:30 pm San Francisco Marriott Golden Gate A1
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In this symposium, various topics associated with SOI process technologies and SOI economics will be discussed.
Silicon-On-Insulator (SOI) technology is regarded as a method to extend the performance improvement of Si technology in addition to that afforded by direct scaling. The performance improvement is a result of the reduction of parasitic capacitance to the substrate and the presence of the floating body during the switching transient.
In addition to performance improvement, SOI allows for a simpler process flow and perhaps even a smaller die size with accompanying improvements in yields. The combined advantages of improved performance, lower integrated processing cost, and a potential transparency to bulk device and circuit design, make SOI a possible replacement for bulk Si substrates in an existing silicon line. However, for this replacement to happen, significant progress in the development of the SOI materials' infrastructure is necessary. Since the second half of 1996, a substantial number of major device manufacturers in USA and Japan have announced their plan to fabricate state-of-the-art integrated circuits using SOI wafers.
Program Co-Chairs: Sookap Hahn, Ph.D., Pacrim Technology Company and Tohru Hara, Ph.D., Hosei University
Agenda
Strategic Directions and Challenges for CMOS Manufacturing on Silicon-On-Insulator (SOI) Substrates: Materials, Device and Process Integration Issues for 0.18 Micron and Beyond Dr. P.K. Vasudev, SEMATECH Market Acceptance of SOI Materials Dr. Robert A. Craven, SiBond, L.I.C. 200 mm SOI Wafers Using the Smart Cut Technology Dr. A.J. Auberton-Herve, SOITEC S.A. New SOI Epi Wafer - ELTRAN Dr. Takao Yonchara, Canon, Inc. Developments in SIMOX-SOI Materials and Manufacturing Michael Alles, Ibis Technology Corporation Applications of Bonded SOI to Ultra-High-Speed BICMOS LSIs Takahide Ikeda, Hitachi, Ltd. Recent Advances on SIMOX CMOS Process Technology for High Speed/Low Power Circuits Keizo Sakiyama, Sharp Corporation Fully-Depleted CMOS/SIMOX Technology for Low-Power, High-Speed ULSIs Toshiaki Tsuchiya, NTT
Who Should Attend: Executive management, sales/marketing personnel, design, manufacturing, R & D, process engineers, and suppliers of equipment and materials, especially those connected with materials technology. |