AMD has the following facilities:
Austin, Texas
Fab 25 0.18 120,000 being converted to flash
Aizu-Wakamatsu, Japan
FASL JV1/(1) 0.35 70,000
FASL JV2/(1 0.25 & 0.35 91,000
FASL JV3/(1) 0.17 118,000 first shipments Q4 of 2001
Dresden, Germany
Fab 30 0.18 -> .13 115,100 ramping up
Research and development at Submicron Development Center, a 42,000 square foot facility located in Sunnyvale, California
Intel has the following facilities:
D1BR - 200,000 sq. ft. (once development, now production)
D1C - 135,000 sq. ft. [.13 -> .10]
D1D - 175,000 sq. ft. [development]
D2 - 36,000 sq. ft. in 1991 [.18/.13] flash
RP1 - 56,000 sq. ft. [development]
FAB1-7 - 435,000 sq. ft. closing next year [.35] flash [edit: 435,000 Rio Rancho+ clean room total includes sq. ft. from old 1-7,9, and the new 11]
FAB8 - ? [.35 and above]
FAB9 - 120,000 flash [upgraded in 2000, still open]
FAB10 - 100,000 sq. ft.? [.25/.18]
FAB11 - 120,000 sq. ft.? [.18 -> .13] flash
FAB11x - 135,000 sq. ft. [.13]
FAB12 - 135,000 sq. ft. [.18]
FAB14 - 90,000 sq. ft. [.25/.18]
FAB15 - 120,000? [.35/25] -> [.18/.13] flash
FAB16 - On Hold
FAB17 - 95,000 sq. ft. [.13]
FAB18 - 80,000 sq. ft. [.18]
FAB20 - 120,000? [.13] Note: Burntolearn claims this is part of D1B
FAB23 - 120,000 sq. ft. [.18] flash
FAB22 - 133,000 sq. ft. [.13]
FAB24 - 135,000 sq. ft. - under construction
Taking into account Burntolearn's comment (giving him the benefit of the doubt) and removing the 435,000 from the FAB 1-7 reference, and excluding FAB24 which is under construction, we get 1,850 sq. ft. of FAB space.
Intel has dedicated development FABs, so most of their production space isn't affected by test runs, development runs, etc. - presumeably, "copy exactly" is good for something, so they should be able to get more wafer starts per sq. ft. than AMD, which is running both production and development (of multiple processes and processors, no less!) at Dresden. AMD had stated capacities of 5K to 6K WSPW at Dresden when it had a clean room space of 90K sq. ft.
Doing the arithmetic, we see that Intel, by that measure, has a maximum, theoretical capacity of 100K to 125K WSPW.
But! Those Dresden numbers are for making CPUs. About 1/3 (wanna_bmw seems to think it's 90%) of Intel (and AMD/FASL) FAB space is used for flash, networking chips, etc, which have only a few layers, meaning that far more wafers can be processed in a given space. So, we should take away a third of those "CPU starts" and double the number, which takes us to about 160,000 wafer starts per week.
Now, most of Intel's FABs are single purpose, dedicated production FABs. Unless Intel is staffed exclusively by idiots, they should be able to lay out their single purpose facilities to get more lines in a given amount of cleanroom space. If we consider the "single purpose advantage" to be save enough clean room space to be worth about 20% in wafer starts, we get to 200K wafer starts per week (divide by .8).
Now, Pete made it crystal clear to anyone with a 3rd grade (or higher) education that the 200K "if every possible wafer were started" figure was 2 to 3 times what would be achieved in practice.
But it looks like that estimated max theoretical capacity was spot on.
Why don't you show us something from Intel, stating their maximum wafer capacity, that contradicts it? |
