"U.S. companies move up to 300-mm wafer fabs"
By David Lammers, EE Times Jul 19, 2002 (7:27 AM)
URL: siliconstrategies.com
DALLAS — After years of fence-sitting, the manufacture of 300-mm wafers is finally taking off in the United States as three of the six largest U.S. semiconductor companies move to the 12-inch wafers at fabs that could alter the landscape in terms of cost-competitiveness.
Texas Instruments Inc. said Wednesday (July 17) it has qualified its 130-nanometer copper process at its new 300-mm facility, DMOS 6, here and is already processing platters. IBM Corp. plans a ribbon-cutting ceremony in the first week of August for its 300-mm fab at East Fishkill, N.Y. And Intel Corp. says it will open its second 300-mm fab, called 11X, in October.
Among the other major U.S. manufacturers, Motorola and AMD are both entering the 300-mm era through partnerships, and Micron Technology is sticking with 200-mm manufacturing for the time being.
IBM puts the cost of its fab at $2.5 billion. TI said the DMOS 6's price tag could not be estimated because the building went up many years ago and the project was completed in fits and starts. Intel won't give the cost of an individual fab.
Keeping such gargantuan beasts fully loaded will be a challenge. A typical 12-inch fab, running 20,000 wafers per month, potentially could spew out nearly 100 million chips a month, a level of demand that even the largest companies may struggle to achieve. During downturns, when loading levels plummet, such large fabs can become a financial deadweight.
Those worries aside, jumping to a larger wafer size is seen as critical to the U.S. industry's historical ability to improve the average cost per function by 25 percent a year, an astounding record that has fueled post-World War II economic growth. The companies that hone their manufacturing skills now could gain a 20 to 30 percent cost advantage over rivals stuck on 200-mm wafers.
Moreover, many industry watchers believe a capacity shortage may develop next year at cutting-edge design rules, largely due to weak 2001-2002 investments.
As Semicon West opened Wednesday (July 17) in San Jose, Calif., Texas Instruments said it has fully qualified its 130-nm copper process at the DMOS 6 facility, where it is now processing about 5,700 of the larger platters per month. The Dallas-based company plans to increase production to 10,000 of the 300-mm wafers per month by year's end.
When fully loaded, IBM Microelectronics' East Fishkill facility — thus far known only as Building 323 — will ramp up over the course of this year to full-scale commercial production by next January. The fab will rival IBM's sprawling 200-mm complex in Burlington, Vt., in terms of production capacity, a spokesman said. Indeed, the abundance of capacity has led IBM to position itself as a leading-edge foundry, soliciting business from the largest fabless semiconductor makers, including Analog Devices Inc. and Xilinx Inc.
Meanwhile, Intel president Paul Otellini on Tuesday (July 16) scotched rumors that Intel was pulling back on its 300-mm program and said the 11X fab in Rio Rancho, N.M., would open in the fall. It will be Intel's second 300-mm fab, after the D1C facility in Hillsboro, Ore., which serves as both a development fab and production facility. D1C has been making Pentium 4 processors since early this year, a spokesman said.
In a conference call to announce weak second-quarter revenue, Otellini said that Intel's 300-mm program remains "strong and on target," despite the company's decision to chop several hundred million from its originally planned $5.5 billion in capital expenditures for this year.
Though rumors swirled, Deutsche Bank analyst's note, that Intel was pushing back orders for 300-mm equipment, Otellini said the plan to cut capital expenditures from an anticipated $5.5 billion to a range of $5 billion to $5.2 billion would not affect manufacturing capacity. The cuts will come from curtailing construction of office buildings, he said, and from asking each engineering department at Intel to forgo the purchase of electronic design-automation tools or instruments.
Intel plans to cut 5 percent from each department's capex budget that way. "We won't touch logic manufacturing," said chief financial officer Andy Bryant. "Instead, we'll trim capex by going from lab to lab saying, 'try to find me 5 percent.' "
Intel will also sponsor an early-retirement program aimed at reducing head count to 83,200, from 88,000 now.
Despite flat revenue over the year, Intel plans to have four 300-mm facilities in operation by 2004, a spokesman said, including two fabs in Oregon, one in New Mexico and another in Ireland. Bryant said he expects the 300-mm ramp to result in efficiencies that will allow Intel to invest less capital for each chip produced. "We won't see those improvements in capital efficiency overnight, but we will see slow improvements," he said.
Clean-slate tooling
Texas Instruments too is looking at gradually gaining a cost advantage over its rivals via 300-mm manufacturing. Larry Tolson, vice president of logic operations, said DMOS 6 started running 300-mm wafers late last year, at 0.18-micron design rules, "just to prove out the equipment." The 2.4-times increase in area for the larger wafers means that TI can place about 5,000 to 6,000 of its baseband processor dice on each wafer, against 1,500 to 2,500 on an 8-inch wafer. Once the equipment is fully shaken out and wafer costs decline over the next year, Tolson said, the switch to the larger wafers will result in production cost savings "in the neighborhood of 30 percent."
Venu Menon, who managed the 130-nm CMOS development program, said TI expects to get better yields with its 300-mm equipment set. "Every time the equipment vendors do a clean-slate design, like they did with the 300-mm tools, we get a lower defect density," Menon said.
Today, a 300-mm wafer is priced in the $350 range and a 200-mm wafer at $75 to $85, said Tolson. But he added that TI expects to see "dramatic" price cuts for 300-mm wafers over the midterm.
TI's strategy is to bring up its 130-nm process at DMOS 6 and at an older fab here, DMOS 4, with mask sets that can be switched between the two.
Tolson said Texas Instruments took a page from Taiwan Semiconductor Manufacturing Co.'s book in two important areas: the use of standard mechanical interface (SMIF) boxes to transport wafers into and out of production equipment without exposure to contaminants, and a switch to scanners from Dutch-based lithography vendor ASML for the 130-nm lines at both DMOS 6 and DMOS 4.
DMOS 6 has 150,000 square feet of Class-100 clean-room space, and Tolson said the use of the SMIF boxes yielded considerable savings on contamination control compared with a non-SMIF environment.
Pioneered by Asyst Technologies Inc., the SMIF approach creates islands of extremely clean air around each tool, and then moves the wafers into and out of the machine automatically through a SMIF interface. DMOS 4 also was converted to the SMIF approach last year, and Tolson said TI plans to use SMIF when it converts its fabs in Miho, Japan, and Freising, Germany, to 130-nm design rules. TSMC adopted the SMIF approach in the late 1980s.
TI, which historically has used Canon and Nikon steppers, made a major shift by choosing ASML lithography tools for DMOS 6 and in the conversion of DMOS 4 to 130-nm design capabilities. "One of the reasons we switched to ASML scanners is that we felt we were at a competitive disadvantage behind TSMC, which was getting much higher throughput — as much as 2x per hour — with its ASML scanners," Tolson said. "We put a lot of study into it before we make that kind of switch."
Spokesmen at Canon and Nikon said new high-throughput scanners will be unveiled when Semicon West reconvenes in San Francisco Monday (July 22) for an exhibit of front-end fab equipment.
TI's strategy is to protect its more-vulnerable customers by keeping smaller-volume products at DMOS 4, which has a backup tool set at the nearby K-fab, and to move high-volume parts — which can be stockpiled in case of equipment glitches — to DMOS 6 and its less-mature tool set. "If a customer needs just one wafer lot of some product, and that lot is delayed, that customer is 100 percent delayed," Tolson said.
Paging partners
Both Advanced Micro Devices and Motorola have opted to march into 300-mm manufacturing alongside partners. AMD plans to jointly operate a 300-mm facility in Singapore with Taiwan-based United Microelectronics Corp., with first silicon likely in 2004. And Motorola has joined hands with three process development partners — Philips, STMicroelectronics and TSMC — in a jointly operated facility in Crolle, France. The quartet plans to begin moving 300-mm production gear next month into Crolle II, which will serve as both a process development center and a production facility, fabricating limited numbers of commercial wafers each month.
A group of 40 Motorola technologists will move to France over the rest of this year to help develop the joint 65-nm CMOS process platform at Crolle II, a spokesman said.
Micron Technology Inc.'s chief executive officer Steve Appleton, meanwhile, recently said that Micron is honing its 300-mm skills at a research line, but has no immediate plans for production. Micron currently can make a fully processed 200-mm wafer for the same cost as a bare 300-mm platter, Appleton said.
Ray Burgess, director of strategy at Motorola's Semiconductor Products Sector, said the company now is flush with capacity at its 200-mm facilities in Phoenix and Austin, Texas. If the existing 200-mm buildings were fully equipped, he said, the semiconductor operation could produce as much as $12 billion worth of semiconductors annually.
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