SI
SI
discoversearch

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor.  We ask that you disable ad blocking while on Silicon Investor in the best interests of our community.  If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.
Technology Stocks : Advanced Micro Devices - Moderated (AMD)
AMD 202.95-16.2%12:03 PM EST

 Public ReplyPrvt ReplyMark as Last ReadFilePrevious 10Next 10PreviousNext  
To: wanna_bmw who wrote (86198)8/1/2002 4:36:35 PM
From: PetzRead Replies (1) of 275872
 
EDITED<<There is no way on earth that a reliable 16-level cell (4 bits) can be made>>

<And why not?? I don't believe you are an expert in this field>

Its an analog technology, so it is 4 times more difficult to double the bits in a cell. Furthermore it gets worse as the feature size (and voltage) get lower. Finally, the decoders (voltage level comparators) would be much slower for 4 bits than for 2.

OTOH, imagine the going from 2 bits per cell to 4 bits per cell in a 2-dimensional area, where each "bit" occupies a different 2-d position. You can double the number of bits and only bring the charges 29% closer to eachother (0.707 x). As I recall, the Saifun method might even use the vertical dimension, in which case doubling the bits has even less effect.

This is a gross simplification, but I am 100% confident that if Intel succeeds in making a 4-bit cell, they will not do it with the same brute-force analog technique. The clock is ticking.

AMD's mirror-bit white paper: amd.com

Petz
Report TOU ViolationShare This Post
 Public ReplyPrvt ReplyMark as Last ReadFilePrevious 10Next 10PreviousNext