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Technology Stocks : Intel Corporation (INTC)

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To: Charles Gryba who wrote (170425)	8/31/2002 8:31:55 PM
From: Tenchusatsu	Read Replies (2) of 186894

C, I think it's the L1 caches, especially the trace cache, that is suffering from thrashing. When you have multithreading, you want your caches to be large and flexible. That's easy for an L2 cache which is easily decoupled from the processor core. But for L1 caches, large and flexible go against the goal of high-speed, which requires the caches to be small and simple. It might help to duplicate the L1 caches to support multithreading in P4. But that would add a significant amount to the die size, and you're that much closer to going with a dual-core design anyway. Tenchusatsu

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