K&S unveils wafer-level packaging technology
By Semiconductor Business News
Sep 16, 2002 (11:05 AM)
URL: siliconstrategies.com
TAIPEI, Taiwan -- During the Semicon Taiwan trade show here today, the Flip Chip Division of Kulicke & Soffa Industries Inc. unveiled its wafer-level packaging technology.
K&S' Spheron wafer-level packaging technology has several advantages over competitive offerings in the marketplace, according to the Willow Grove-based company.
Compared to conventional chip-scale packaging, for example, Spheron delivers improved coupling capacitance, “because the under bump metallization (UBM) and solder structure reside on top of a 5 micron low-k dielectric film,” according to K&S.
Reliability is also enhanced by more than 30% because the UBM and solder structure reside on top of a planarized polymer film. This eliminates poor metal step coverage and associated topology issues in conventional wafer-level packaging technologies, the company said.
Spheron technology also improves thermal cycle reliability by more than 30%. “We expect Spheron technology to find wide application in performance memory and RF applications, which will benefit from the enhanced performance and cost,” said Scott Barrett, product manager for K&S, in a statement.
Separately, K&S introduced DuraPlus, a fine-pitch epoxy probe card developed to increase bond yields. Pad pitch capability to 45 micron (in-line), 30 x 60 micron 2 row or 40 x 80 micron 3 row stagger are currently available. |
