Catalyst Semiconductor Sets Sight On $325M SPI EEPROM Market
SUNNYVALE, Calif.--(BUSINESS WIRE)--Oct. 3, 2002--Catalyst Semiconductor (Nasdaq:CATS) today announced it has completed qualification and released to production one of the most complete families of high-speed serial EEPROMs with an SPI(TM) interface in the industry. "Market projections show that SPI interfaced EEPROMs should represent one-quarter of the serial EEPROM market in 2005. This represents a $325 million3 opportunity," said Catalyst Product Marketing Manager Gary Craig. "The high-speed serial SPI interface is preferred over parallel interfaces in applications where speed, board density and low costs are crucial. Data communication and automotive applications are particularly well suited for SPI EEPROMs."
Key Family Features
-- Highest Speed Performance
- 10MHz: 1kbit through 64kbit densities
- 5MHz: 128kbit and 256kbit densities
-- Versatile 3-bit Block and Write Protection
- 10MHz: 1kbit through 64kbit densities
-- Standard and Improved 2-bit Block Protection
- Standard 2-bit block protection
- Enhanced 2-bit block protection with software
write protect enable
-- Broadest Operating Voltage Range: 1.8volts to 6.0volts
-- Lowest Power Consumption: 1microampere Standby Current
-- Support for All SPI Clock/Phase Modes
Catalyst's SPI family consists of 19 devices with memory density ranging from 1kbits to 256kbits. Speeds are 10MHz for all devices except the 128kbit and 256kbit devices that operate at 5MHz. Devices with standard 2-bit block protection, enhanced 2-bit block protection with software write protection and versatile 3-bit block protection with software write protection are offered. All four SPI clock/phase modes -- 00, 01, 10 and 11 -- are supported through factory programming options.
Innovative Block Write Protection Methods
Catalyst offers three block protection options:
-- Standard 2-bit block write protection
-- Enhanced 2-bit block write protection with software write
protect enable
-- Versatile 3-bit block write protection with software write
protect enable
A new 3-bit block write protection capability is available for the 1kbit through 64kbit density devices. A status register with three block protection bits makes single-page write protection possible. To write protect a small section of memory to hold, for example, a serial number or system ID, a large section of memory does not need to be locked. Single-page write protection uses the memory array efficiently and is especially important with higher density memories.
The write protect enable bit, WPEN, within the device status register, allows software control of the memory array's write protection. Write protection works with the hardware write protection pin to define which memory array segment is write protected.
In addition, by using the write protect pin and WPEN, a device can be made to appear one-time writeable. Details are given in Catalyst's Design Note 8, which is available at catalyst-semiconductor.com.
New Low Density SPI EEPROMs
The most recent SPI EEPROMs introduced focus on lower density memories with 3-bit block write protection and software write protect enable.
Part Density Block Write Protection
2-bit 3-bit
CAT25C01 1 kbit Yes
CAT25010 1 kbit Yes
CAT25C11 1 kbit Yes
CAT25C02 2 kbit Yes
CAT25020 2 kbit Yes
CAT25C03 2 kbit Yes
CAT25C04 4 kbit Yes
CAT25C05 4 kbit Yes
CAT25040 4 kbit Yes
www.catalyst-semiconductor.com/eeprom. Prices depend on memory density and start at $0.26 in 10,000 piece quantities. Devices are available for sampling and production. |
