SI
SI
discoversearch

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor.  We ask that you disable ad blocking while on Silicon Investor in the best interests of our community.  If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.
Technology Stocks : Silicon Graphics, Inc. (SGI)
SGI 84.640.0%Nov 20 3:59 PM EST

 Public ReplyPrvt ReplyMark as Last ReadFilePrevious 10Next 10PreviousNext  
To: Jerry Whlan who wrote (1914)7/22/1997 8:10:00 AM
From: Alexis Cousein   of 14451
 
>The MIPS roadmap had H1 with a bandwidth of 5GB/s, the R12k uses the >same bus as the r10k which is 64-bits at 100MHz, or 800MB/s peak. >Unless the spec for r12k has changed, there is certainly a major
>descrepancy here.

Only if you have a machine architecture that's appropriately aggressive, too. There's more to a machine than just a CPU (certainly if you're talking about the I/O side of a CPU).

And whether we like it or not, machine architectures tend to stick around for longer than CPUs.

That accounts for the discrepancy between many of the SPECint/fp95 `chip' theoretical numbers and actual numbers measured in machines of one of our competitors ;). Especially SPECfp95, which is a lot more memory-bound than SPECint. And SPECfp95 isn't really what I'd call a real-world application either ;).
Report TOU ViolationShare This Post
 Public ReplyPrvt ReplyMark as Last ReadFilePrevious 10Next 10PreviousNext