Industry's First 1:4 LVPECL & LVDS Fanout Buffers With Internal Termination Accept Any Differential Input
Friday November 1, 12:16 pm ET
- Highest throughput: >2GHz - Lowest jitter: <1ps pk-pk - Lowest skew: <20ps - Smallest package: 16-pin (3mm x 3mm) MicroLead Frame(TM) (MLF) package
biz.yahoo.com
SAN JOSE, Calif., Nov. 1 /PRNewswire-FirstCall/ -- Four new high-speed, LVPECL and LVDS clock fanout buffers for the ultra-low jitter and skew requirements of SONET/SDH communications systems, high-end enterprise server applications, and ATE systems have been developed by Micrel Semiconductor (Nasdaq: MCRL), an industry leader in the design and manufacture of integrated circuits for the high-speed communications, analog and power management markets.
The latest additions to Micrel's Precision Edge(TM) Timing & Distribution family, the SY89831, SY89832/3, and SY89834 are high-speed, precision LVPECL and LVDS 1:4 fanout buffers. The devices are designed with a unique input stage that includes internal termination and the ability to accept any differential input source, whether the input signal is AC-coupled or DC-coupled. No external components are required in the signal path. Stubs associated with external termination networks are eliminated, thus preserving signal integrity.
The SY89831U operates from a 2.5V or 3.3V supply and is optimized for applications that require up to four precision LVPECL outputs. Skew within the device is guaranteed to be less than 20ps, and rise-and-fall times are less than 225ps. The SY89834 is optimized for applications that require LVPECL outputs from a single-ended LVTTL/CMOS source. For applications that require LVDS outputs, the SY89832 operates from a 2.5V supply, and the SY89833 operates from a 3.3V supply. Unlike other LVDS buffers, the SY89832/3 feature rise and fall times as low as 190ps -- the fastest edge rates in the industry.
The SY89831 family is optimized for all communications applications, including all SONET/SDH, Gigabit Ethernet, and Fiber Channel clock trees. Designed for communications applications, the family features a total jitter (the amount of peak-to-peak jitter measured over 10^12 clock cycles) of less than 1ps over the device's full temperature and voltage ranges. In addition, the SY8983x family are offered in a 16-pin (3mm x 3mm) package, which represents a 70% reduction in footprint area compared to alternative solutions. |
