Subject:
Synopsys and Precedence Deliver Mixed-Signal Co-Simulation Solution for
Verilog-XL; Faster, More Accurate Simulation for Full System-on-a-Chip
Designs
Date:
Mon, 4 Aug 1997 06:17:25 -0700 (PDT)
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News Alert from BusinessWire via Quote.com
Topic: Mentor Graphics Corp
Quote.com News Item #3618016
Headline: Synopsys and Precedence Deliver Mixed-Signal Co-Simulation Solution
for Verilog-XL; Faster, More Accurate Simulation for Full System-on-a-Chip
Designs
======================================================================
CAMPBELL, Calif.--(BUSINESS WIRE)--Aug. 4, 1997--Synopsys, Inc.
(NASDAQ:SNPS) and Precedence, Inc. today announced a faster and more
accurate full-chip mixed-signal co-simulation solution.
The new solution links Verilog-XL to the Synopsys leading-edge
timing, power and analog analysis engines. Designers can now
concurrently simulate a mix of behavioral, register transfer,
transistor and analog levels with exceptional runtime performance and
deep submicron accuracy. This rigorous mixed-signal, mixed-level
Verilog simulation requires the jointly developed Vertue product, and
TimeMill or PowerMill enhanced by the new Analog Circuit Engine (ACE)
built by EPIC Technology Group, a division of Synopsys.
"This is great news for high-level design engineers in the
Verilog market who don't typically work at the transistor level,"
explains Gary Larsen, senior vice president and co-general manager of
EPIC Technology Group.
"With the shift to system-on-a-chip IC design, more and more
Verilog designers are finding that they now have a couple of
transistor or analog blocks in their designs. Our Vertue solution is
a very simple way to deal with these blocks. Vertue adds a few lines
of commands to the Verilog command file, then synchronizes the
simulation of the different blocks through the entire simulation run.
It eliminates the need for a designer to be an analog design expert
in order to achieve complete verification results."
"One of the often overlooked side effects of the reinvention of
the RTL methodology is the automation of analog design," said Gary
Smith, EDA analyst at Dataquest. "With the advent of system-level
integration, it has become imperative to use analog system-level
macros as part of your ASIC solution. This means that analog
simulation must become part of your verification strategy.
"EPIC used Precedence's SimMatrix backplane in introducing Vertue
which allows the user to co-simulate at the behavioral and switch
levels and now, with the addition of ACE, at the analog level. This
will become a must-have tool for ASIC designers in the next few
years."
System-level integration is intensifying and the need for fast,
accurate verification of mixed-signal integrated circuits (ICs) is
now an acute design issue. A typical design's analog content is
rapidly increasing -- according to Dataquest, approximately 40 percent
of new ASIC designs will have analog content. Within three years, 70
percent of all ICs will contain analog components. The combination
of Vertue and TimeMill or PowerMill with the mixed-signal ACE option,
is a powerful solution for verifying system-on-a-chip designs.
Through Vertue, ACE helps Verilog users manage mixed-signal,
crosstalk effects and reduce power consumption in IP cores and analog
and memory blocks for system-on-a-chip designs. ACE is an option to
TimeMill and PowerMill, which provides greater speed, accuracy and
capacity for transistor level IC simulation.
About Vertue
Vertue enables co-simulation of EPIC's TimeMill or PowerMill
design analysis products with Verilog-XL. Vertue is used by IC
designers to perform full-chip functional, power and timing analysis
of mixed-signal designs. Using the SimMatrix backplane developed by
Precedence, Inc., Vertue synchronizes the simulation of different
blocks through the entire simulation session.
Precedence's SimMatrix simulation backplane enables the
co-simulation of two or more simulators. The backplane's scalability
gives the user an "integrate once" model that, with a single
integration to the backplane, immediately enables access to each
simulator already integrated into SimMatrix.
About Precedence
Precedence, Inc. is a pioneer and leading provider of
co-simulation solutions to designers of electronic integrated
circuits, printed circuit boards and systems. Through the SimMatrix
simulation backplane, designers can seamlessly combine and
concurrently apply simulation tools from Analogy, Cadence,
Chronologic, EPIC, IBM, IKOS, Mentor Graphics, Quickturn, Vantage,
Viewlogic and Zycad.
Precedence distributes its solutions worldwide through partner
companies and direct distribution channels. A wholly-owned
independent subsidiary of Mentor Graphics, Precedence is
headquartered at 1700 Dell Avenue, Campbell, CA 95008. Phone:
408/345-4880, Facsimile: 408/345-4884. The Company's World Wide Web
site is precedence.com .
About Synopsys
Synopsys, Inc. (NASDAQ:SNPS) is a leading supplier of electronic
design automation (EDA) solutions to the global electronics market.
The company provides comprehensive design technologies to creators of
advanced integrated circuits, electronic systems, and systems on a
chip. Synopsys also provides consulting services and support to its
customers to streamline the overall design process and accelerate
time to market. Additional information about Synopsys is available
at www.synopsys.com .
CONTACT: Precedence, Inc.
Lorie Bowlby, 408/345-4880
lorie@precedence.com
or
Synopsys, Inc.
Lisa Washington, 415/694-1853
lisaw@synopsys.com
KEYWORD: CALIFORNIA
INDUSTRY KEYWORD: COMPUTERS/ELECTRONICS COMED TELECOMMUNICATIONS
INTERACTIVE/MULTIMEDIA/INTERNET PRODUCT
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