Thanks for the tip, Allen. Here's the whole story. I don't mind waiting a little longer. The endorsement by Samsung more than makes up for it.
By David Lammers
EE Times
(06/23/03 10:11 a.m. EST)
Kyoto, Japan - Phase-change RAM, also known as ovonic or chalcogenide memory, appears to have gotten a new lease on life.
Recent wisdom had been that yield issues, related to the heat-up cycle required to change the phase of the ceramic materials, had all but killed PRAMs' competitive chances against nonvolatile memories based on ferroelectric or magnetic materials. But now Samsung Electronics Co. Ltd.-the largest memory vendor, by a wide margin-has publicly endorsed the approach's "strong potential" as a next-generation nonvolatile memory.
And Intel Corp. vice president of technology Stefan K. Lai told EE Times that while the timetable has slipped on Intel's ovonic unified memory research program, the effort remains very much alive.
At the 2003 Symposium on VLSI Technology here earlier this month, Samsung (Seoul, South Korea) presented three papers on PRAM. Phase-change memories use current to heat up a ceramic alloy of germanium, antimony and tellurium: Ge2Sb2Te5, or GST. A bit is represented by changing the phase of the GST chalcogenide material from a resistive amorphous state, referred to as the reset state, to a crystalline state, called the set state. Samsung's approach uses a twin-cell scheme in which 1 bit is physically represented by a combination of one crystalline and one amorphous cell.
Samsung engineer Y.N. Hwang said Samsung used quarter-micron CMOS technology to create a test array that integrates one CMOS switching transistor with a chalcogenide memory element. The threshold voltage was set at 1.1 V, high enough to prevent a read disturbance. Samsung engineers varied the write times and concluded that it is possible to operate the device at 100-nanosecond pulse durations.
They also studied PRAMs' reliability and retention times-two key attributes for any nonvolatile technology-and concluded that both can be improved sufficiently to give PRAM "strong potential" as a next-generation memory, Hwang said.
The Samsung team conducted an endurance test of 1.8 x 109 write cycles and observed no failures up to 1.58 x 109 cycles. Because the read cycle in a PRAM is partially destructive, the Samsung team also tested the read-cycle endurance. Those tests found that "one of the major failure mechanisms is a small set/reset resistance ratio due to incomplete phase transition of the GST material." The read endurance reached 105 cycles.
Optimally, endurance of 1017 or more cycles is sought for DRAMs and SRAMs that will be employed in commercial applications.
By thermally stressing the test array, Samsung concluded that at 85 degrees C, the cell data retention time would be about two years. By doping the GST material with nitrogen, retention times could be sharply improved, to 10 years, according to the team.
Samsung tested various cell sizes and reset currents, with the smallest being 0.32 micron x 0.32 micron (0.1024 square micron) at 2 milliamps.
A separate Samsung team reported on an edge-contact-type PRAM that it claimed considerably reduces the amount of current required to write a cell.
Samsung also said at the symposium that it has programs under way to develop nearly all of the emerging memory types. For example, the company presented a 32-Mbit ferroelectric array that addresses the fatigue problems plaguing FRAM. Those problems have led some to question whether FRAMs have the endurance properties required for use beyond cell phones, where the number of erase and write cycles is much smaller than in computer or industrial applications.
And at the International Solid-State Circuits Conference in February, Samsung engineers discussed its magnetoresistive-RAM development program. Issues for MRAM are whether the cell size can be reduced enough to let MRAM compete with flash, FRAM and DRAM and whether the write current ever can be made low enough to suit mobile applications.
Adjusted expectations
Intel's Lai, who oversees its flash manufacturing and technology programs, said that when Intel first started its ovonics program several years ago, the cost projections showed ovonic-type memory "compared favorably" with flash on a cost-per-bit basis.
Rumors subsequently swirled about "zero" yields for ovonic memories. Asked by EE Times whether they were true, Lai said only that Intel remains convinced the basic technology has merit.
"There is no question that ovonics works as a memory," Lai said. But he added that Intel would "need to reduce the cost much further before we can position ovonics as a replacement for StrataFlash."
StrataFlash is Intel's 2-bit/cell floating-gate flash technology. Intel is pushing StrataFlash for data storage and code execution applications, including an investigation of "data friendly" architectures that strip off the pulse write and other peripheral circuitry to make StrataFlash more cost-competitive with NAND-type flash.
To be sure, floating-gate flash is likely to run into scaling issues, starting with a moderate hit at the 45-nanometer node and then worsening at the 32-nm node, Lai said. The industry has yet to find a high-k dielectric material that can be used for the capacitor at those design rules, and scaling the channel becomes problematic.
Still, the cost issue has "pushed ovonics further out-five years out and further," Lai told EE Times.
"We had too-high expectations for ovonics. We were looking for a low-cost replacement for StrataFlash, but we have not found the magic bullet. We have had to learn some hard facts," he said, declining to be more specific.
At the same time, Intel has not replaced ovonics with another unified-memory approach. Lai said that Intel is approached often with alternative nonvolatile memory technologies and that it has closely studied nearly 20 proposals, including silicon oxide nitride oxide silicon (Sonos)-type flash structures. Intel does have another, longer-term memory research project under way that is looking at polymer memories.
As evidence that Intel is continuing its development of ovonic memories, Lai said the program recently was moved in to the DC1 development fab in Santa Clara, Calif. "We don't make a move like that without studying very carefully whether the new materials will have an adverse impact on processes in the fab," he said.
"With ovonics, we believe we have an idea how to reduce the costs, but we could not disclose that now. When we are ready to talk about it, the industry will be surprised, I promise you," Lai said.
Intel does not believe that MRAM will ever be introduced into the mobile-systems market, because of the relatively high write currents required to flip the magnetic tunnel junction, he added. And while FRAM is a low-power technology, the cell size may not be very scalable, as with flash. Since Intel already has a major business in flash, it does not need FRAM as well, Lai noted.
"The top Intel executives ask me almost every day what we have in line when flash is no longer scalable," he said. "One thing is for sure: We don't want to invest in a one-generation technology."
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