Technology Focus: ASICs: Gearing Up For
Systems-On-Silicon Market
With a new generation of highly integrated, high-volume designs up for grabs, ASIC
vendors are ramping up their manufacturing processes, extending their core libraries,
and refining their design methodologies.
Riding a wave of deep-submicron process enhancements and the availability of a
growing array of synthesized cores, designers are for the first time seeing the
potential of systems-on-a-chip integration. Core-based methodologies offer a surefire
way to maximize design reuse and meet shrinking time-to-market goals.
"The potential growth in this market is much, much higher than for traditional ASIC
or standard parts, because it offers the designer much more flexibility," said
Behrood Sarhoomand, vice president and general manager for system solutions at
Fujitsu Microelectronics Inc. , San Jose.
But it remains to be seen exactly how the market will manifest itself and what role
ASIC vendors, independent intellectual property (IP) suppliers, and electronic design
automation (EDA) tool vendors will play as the market unfolds. What is clear,
however, is that the average density of ASIC designs is rising rapidly.
"Not long ago, when we talked about system-level chips, we were talking devices with
more than 100-K gates," said Ted Latrell, program manager of the ASIC core program at
IBM Microelectronics in Essex Junction, Vt. "This year, we expect our system-level
designs to average over 700-K gates, and we're working on [technology] with greater
than 2. 1 million gates."
That kind of density requires a core-based approach, said Dushyant Desai, director of
strategic marketing for VLSI Technology Inc., San Jose. "You don't have any choice if
you want to simplify design and verification and retain your time-to-market
advantage."
A key enabler to the systems-on-a-chip market has been ongoing enhancement in process
technology. Virtually all ASIC manufacturers are running 0.35-micron processes, and
most plan to offer silicon in 0.25-micron CMOS in the near future.
Market leader NEC Corp. launched commercial production of ASICs with a 0.25-micron
drawn channel length earlier this summer at its Hiro- shima, Japan, fab. ASICs
fabricated in the process operate on-chip at 250 MHz, compared with 130 MHz for the
company's 0.35-micron designs.
NEC is initially offering a library of memories and other standard products, and will
add a family of MIPS R4000-based cores by year' s end.
Some ASIC vendors have already announced plans for moving to 0.18 micron. Earlier
this year, LSI Logic Corp., Milpitas, Calif., announced its G11 ASIC line with an
effective gate length of 0.18 micron. The product will support extensive mixed-signal
capabilities, on-chip memory, and up to 8.1 million usable logic gates.
LSI has also added to G11 a new design concept, called the mix-and- match
architecture. It is based on two cell architectures: one optimized for performance,
and the other for density.
The architecture will allow designers to optimize their designs for minimum power
consumption and maximum performance by mixing and matching libraries on a single
chip. Cores or other partitioned blocks can be implemented in either library and then
dropped into the appropriate random-logic "fabric."
In the next two years, analysts expect the industry to move to 0.18 micron. But to
capitalize on the higher densities, designers will have to dramatically alter their
approach to chip design.
"People are moving from a silicon-craftsman mentality to a system- integrator
mentality, and a lot of them are in this middle space in what I would call
'overwhelmed silicon craftsman,' where they're still trying to do things the old way
and they're finding out that everything' s breaking," said Steve Glaser, vice
president of marketing for system- on-a-chip at Cadence Design Systems Inc., San
Jose.
Chip design in the systems-on-silicon world will become much more like today's
PC-board design: Virtual components, or IP blocks, will be used on a chip just as
physical components are combined on a board, observers said.
"Designers have to move more toward being a system integrator, where they focus on
integrating those already-completed components and verifying that the interfaces
work," Glaser said. "That's what a board guy does, and that's what a chip designer
will have to do in the future as the PC board becomes the silicon substrate."
While in-house development is their primary focus, most ASIC vendors are open to the
idea of licensing some cores from independent IP suppliers. "We're extremely rich
when you look at us from a core point of view, so a good portion of our libraries
will come from internal sources, " Fujitsu's Sarhoomand said. "But there are some
solutions in the market that have become de facto standards, and we're not planning
on reinventing the wheel, so we'll have a mix of both."
Fujitsu is planning a major announcement on its systems-on-silicon capabilities in
the fourth quarter.
Toshiba Corp.'s focus is on developing cores for many applications, including
networking, 3-D graphics, set-top boxes, and hard drives.
Toshiba recently broadened its core library for networking applications with a MAC110
ASIC core cell licensed from Packet Engines Inc. Targeted at Fast Ethernet switches,
multiport bridges, routers, and hubs, the MAC110 is a 10/100Base-T Ethernet media
access controller core that features wide support for physical-layer devices at
10-Mbit/s and 100-Mbit/s speeds.
While Toshiba is licensing some cores from third-party vendors, it plans to develop
most of its I/O cells in-house. "It makes more sense to have more control over those
because they're analog-intensive and process-specific," said Shawn Worsell, product
marketing manager for Systems IC Division product marketing at Toshiba America
Electronic Components Inc., Irvine, Calif.
IBM Microelectronics has made a major effort in the merchant ASIC market since its
entry in 1993. With its external business growing rapidly, the company expects to see
its ASIC business about evenly split between merchant and internal customers in the
next few years.
IBM initially scored in the data-processing arena, but the company has since
broadened its systems-on-silicon core offerings to include communications and
consumer markets. Its present library includes a wide range of cores in each market
area, a number of cross-segment peripherals, and variants of the PowerPC401. The
library is growing rapidly. At the recent Custom Integrated Circuits Conference, IBM
added 50 more functions.
"It was obvious that once the industry went below 0.5 micron, you could put a lot
more functions on-chip, but designers weren't going to be sitting there designing 1,
2, or 5 million gates," Latrell said. "We knew the technology limitations were going
to go away, so we put in place a methodology whereby our designers can take
microcontrollers, microprocessors, and other high-level functions and productize it
to make it available as just another element, much like we've done in the past with
primitive elements for glue logic."
Most of IBM's functions were developed in-house, and that is unlikely to change
significantly, Latrell said. "The issue with IP is if you license a function, you
have to pay a royalty on it, and you have to put that into your chip price."
Japan's Hitachi Ltd. is using its HG73C series 0.35-micron cell-based ICs to offer
ASIC integration capabilities for systems-on-a-chip designs for portable
information-processing products, multimedia systems, and commercial and industrial
equipment. The HG73C series features more than 600 standard cells and approximately
200 I/O cells.
Hitachi recently added two CPU cores to the family: the H8S, a 16- bit CISC
microprocessor, and the SH-3, a 32-bit RISC engine that supports Windows CE.
The core development effort at VLSI Technology is primarily focusing on
communications, consumer digital entertainment, and home computing.
In the communications arena, the company's cells support most major standards,
including GSM, Digital European Cordless Telecommunications (DECT), Personal Handy
Systems (PHS), and Code Division Multiple Access. VLSI has recently announced a
family of single-chip PHS baseband processors for base-station applications and the
first DECT baseband processor to offer ISDN capability.
In consumer digital entertainment, VLSI is targeting cores and standard products for
network-interface modules for both satellite and cable services. The entertainment
offerings include controllers based on the ARM microcontroller from Advanced RISC
Machines Ltd., Cambridge, England, for set-top-box designs and MPEG-2 decoders for
back-end functions.
The focal point for VLSI's set-top-box effort is its VLSI Integrated Set-Top
Architecture, a suite of digital video devices, application programming interfaces,
and reference platforms. VLSI's home-computing effort leverages the company's
extensive background as a former supplier of PC chip sets. It has licensed Hitachi's
SH-3 and SH-4 microcontrollers as well as the ARM processor.
As the market moves to a systems-on-silicon focus and the number of independent IP
suppliers expands, EDA tool vendors are in a unique position. Some plan to offer
cores.
In the last year, Mentor Graphics Corp., Wilsonville, Ore., has acquired several
suppliers of "soft" cores and bought the rights to distribute an MPEG-2 core
developed by Sarnoff Labs. Mentor has also formed a business unit, called Inventra,
to manage its IP products.
Synopsys Inc., Mountain View, Calif., has purchased the cell-based array technology
of Silicon Architects.
And at the Design Automation Conference this year, Mentor and Synopsys announced a
partnership to endorse a single design reuse methodology for IP.
Cadence has a different strategy: to stake out a position as an enabler, or
"realizer," of system chips. Key to that focus is the development and acquisition of
tools and technologies tuned to the system-chip paradigm. As designers have moved to
increasingly complex ASIC designs, verification has become a key bottleneck, one that
calls for a new methodology, Glaser said.
"Rather than use an 'ASIC-out' methodology, where you look at the ASIC and then look
at the outside boundaries of the ASIC, you need to have a systems model, or what we
call a 'systems-in' methodology, in which a system model is created first," he said.
Cadence recently announced an Open Modeling Interface (OMI) link between the
company's system-level simulation tools and HDL simulators. Submitted for IEEE
standardization, OMI is a simulator-independent interface that lets tools exchange or
cosimulate models.
The best hope for a flourishing market of independent IP vendors is standardization,
and the leading industry effort to build those standards has clearly been the Virtual
Socket Interface (VSI). Launched last year as a coalition of EDA, semiconductor,
systems, and IP vendors, the VSI Alliance is attempting to develop standards that
will allow designers to mix and match IP from various sources.
The group's first spec defines IP standards for common sets of deliverables,
interfaces, and data formats. Its eventual goal is to make cores so portable that
designers can use a Web-based database to quickly identify IP sources, evaluate
performance and cost trade-offs, and complete the transaction for design-in.
Whether such an ideal environment can be achieved remains to be seen. And even if it
can, many ASIC vendors question whether designers will be willing to accept the risks
associated with mixing and matching IP from various sources and taking the solution
to an independent foundry.
Customers need to ask how much of their staff they want to devote to building
solutions, and how they can be sure the solutions will work and be fully compliant,
when they could have it done by ASIC vendors, Toshiba's Worsell said.
"We just think the picture being painted of a plug-and-play world, where you're going
to be able to order and purchase IP over the Internet, just isn't going to happen,
primarily because of the complexity of designs," VLSI's Desai said.
He believes that no plug-and-play standard will obviate the demand for architectural
customization and optimization and the kind of systems expertise ASIC manufacturers
have traditionally supplied.
"My experience over the last 10 to 15 years has been that no matter how small the
geometry, your performance and density requirement will always be at the cutting
edge," he said. "So you'll never be able to freely or inefficiently use silicon."
-John H. Mayer is a freelance writer based in Belmont, Mass. |
