Dear Dan3:
With all of the public discussion of what may have gone wrong with Intel's 90nm CPUs, I have come to a theory that fits all the facts. That is that Intel's R&D process researchers evaluated the new 90nm process using the current at that time test and measurement standards to produce the standard characterizations. All 90nm CPU designers used that set of characterizations to design their CPU models, Prescott, Celeron and Dothan.
After all the steps that lead to tapeout and real silicon implementations of their CPUs, a huge problem appeared, even though they worked, they were using too much power. 50% too much! The problem was quickly traced to static power consumption (leakage). The process guys found that the standard characterizations missed a leakage mode insignificant at standard sizes that was very significant at the custom sizes typically used by the designers. Adding that new mode into the models nearly matched the the real world results.
The CPU designers tried a quick fix using the new models but, the real world again showed that the leakage mode has a knee more striking than realized and they had to come to the conclusion that a quick fix was not likely. They went down and reworked the design and it needed a complete retest in the Dothan and Prescott range because they needed a new tape out. The Prescott hacked (stripped of leaky L2 cache sections) to be like the value line Celeron meets the target power envelope of that version at reduced clock rates so that these dies could be salvaged.
Now the new tape outs have happened and they are trying to fix them back to working states but, a new respin is currently needed (known at the CC). Figuring that this will be successful, production starts in late November and will be available for introduction (paper launch (rocket lot parts)) in December. Volume must wait for normal lots in February. If the new spin doesn't fully work, they have the margin for one new respin and may have to launch volume in March yet make a December introduction (paper launch).
Yes, the Process guys and the Designers may finger point with the Designers saying, "The process guys failed because they sent incomplete characterizations, so its a process problem". The Process guys respond with "The designers misused the characterizations by using transistor designs out of ranges covered by the characterizations!" "If they would use more standard transistors instead of these weird custom ones in their designs, the CPUs would perform as expected, so its a design problem!"
Well they are both right, but the real answer is that the cutting edge is fraught with these problems and slippage is normal. Its just so much more in the spot light!
The end result is that both Dothan and Prescott won't make it till at least late Q1. When they are introduced, figure two to three months to real start of a volume ramp. Of course the sword of "rocket lots not matching production lots" could extend these to 5-6 months as happened to AMD in the 400MHz K6-2/3 days and Intel in the 1GHz P3 days.
Pete |
