A Conversation with Dan Dobberpuhl - Part 2
DITZEL So will that change who is willing to go to the newer technologies and how fast they'll go to it? I've heard that as people are switching from today's technology—where we're currently at about .13 microns—as we go into 90- and 65-nanometer here, that maybe it's going to be a different kind of customer who will go there first.
Maybe it won't be the standard company doing ASICs [application-specific integrated circuits] that will go, but somebody else. How do you think it's going to shift the patterns of usage?
DOBBERPUHL It's hard to say. There's a slowdown in the rate of transition to the more advanced technologies. It's caused by a number of factors, including the technical design issues—of which the leakages are a very significant one. There are others as well. Also, as just a financial issue, mask costs are extraordinarily high below 0.1 micron—on the order of $1 million for one mask set.
The Future
DITZEL Where do you see technology taking us? Today I guess one of the complaints we have is people have PCs with four or five fans in them when the CPUs are dissipating 50 or 60 watts. Should we expect that our PC desktops are suddenly going to turn quiet in the next 12 months? Or are people going to use more power to get higher megahertz. What do you have in your crystal ball for the next five years?
DOBBERPUHL I think you're in a better position to answer that than I am, Dave. This is a kind of a marketing and business trade-off. There are a bunch of technical constraints, and right now we do the best we can within those constraints.
You can have high performance or you can have low power or you can have a combination. But you can't have the extreme of either. So how you choose to parameterize a given system is really a function of what you think the customer wants.
DITZEL I think it's almost a psychological factor of when people believe they have enough performance. Because if they don't have enough, they're going to push for higher and higher megahertz, which is probably going to come at the expense of power continuing to go up. But wouldn't it be true that once people feel like they have enough performance, if you just need to sustain the performance levels, technology goes forward. Shouldn't that give us opportunities to reduce power?
DOBBERPUHL No question about it. If all you want to do is sustain current levels of performance, then advances in technology make that easier and easier. The problem comes when you try to extract the maximum amount of performance from the advanced technology.
DITZEL So I guess—given the operating system you have today and maybe the PC you have today—if you're happy with the performance, the real problem for business is you're not buying a new PC or a new operating system.
In some sense one can say that the people who design operating systems and new processors are looking for ways that you won't have sufficient performance with the machine you have today, so that you'll need to buy something new. Is there any way out of this vicious cycle?
DOBBERPUHL I don't know. From an engineering point of view, we'll continue to try to improve the performance-per-watt ratio. It's interesting that a low-power processor can deliver on the order of 1,000 MIPS per watt. And maybe 2,000 for a really good one. It depends upon the absolute performance level.
And the high-performance processors are about an order of magnitude worse than that. They're on the order of 100 MIPS per watt. So there's a huge spread, and that's mostly a function of the same things we were talking about earlier with the Alpha and StrongARM.
It's where you choose the design point—whether you go with 100 million transistors or 20 million transistors and whether you choose two gigahertz or one gigahertz. These things are all parameters the designer chooses, but then he has to live with the consequences.
DITZEL When you build chips, do they all come out at the same speed and the same power?
DOBBERPUHL Don't we wish? The semiconductor process variation is quite wide and follows a statistical distribution that designers target anywhere from three to six sigma points of the variations, depending on what kind of yield they want to get. In terms of frequency, it's not unusual to have a 40 or 50 percent spread from the slowest to fastest coming out of the same process line.
DITZEL So you could actually think of buying a computer, and one might have a different battery life than another just because of the distribution of chips and how they're made.
DOBBERPUHL Absolutely. The power dissipation varies, just as the performance does. The dynamic part of power dissipation is not that variable. But the static power dissipation is highly volatile and can vary dramatically from device to device.
DITZEL I notice you have a PDA device with you here. It seems to me in many ways people had to change the operating system and the user interface with PDAs because they couldn't fit what was in their PCs into something that was handheld. Do you think we'll be able to get the performance of a desktop PC into your hand in a few years?
DOBBERPUHL To a large degree, yes, I do. I think it's mostly going to come from design finesse—somewhat from technology, but just a lot of continuing design development because we're kind of at the wall in terms of the physics.
I/O Power Consumption
DITZEL One of the other issues for power is not only the power the chip consumes computing things, but also the power it takes communicating to the other chips on the board—the I/O power. Are we going to have to do something about that problem in the future as well? For example, will we have to do more integration on chips? How do we get I/O power to go down?
DOBBERPUHL Yes, I/O power is an issue. And I think it's a piece of a bigger issue, which is system-level power overall. We've been concentrating primarily on microprocessors, but really the same issues apply to all silicon chips.
People have spent many years doing system architecture and micro-architecture based on performance. Now I think it's very relevant to look at system architecture from a power point of view. And it may cause us to make some changes in the way we architect systems. We design memory systems to optimize performance. In these power-constrained systems, it makes a lot of sense to design memory systems to optimize power, or a combination thereof. So I think, then, the same thing goes for I/O.
Off-chip clock rates in the last few years have increased dramatically with the DDR [double data rate] concepts and things like that. Consequently, power has increased as well. Managing I/O power is an issue, and again it's the kind of physics issue that can't be avoided, and so it behooves the designers to deal with it and make trade-offs.
DITZEL One of the things I've heard is that in order to reduce I/O power, people are moving to the system-on-a-chip approach where the functionality of many chips is integrated into one. How does that affect the design challenge? I presume it's harder to design one mega-chip than individual chips with many fewer gates per chip.
DOBBERPUHL Well, you're absolutely right in terms of integration saving power. You can save a lot of power if you can move interconnects from chip-to-chip to on-chip.
You can have higher performance as well. So it's a double win. But the problem is that as you integrate more functions onto a chip, the design problem grows somewhat linearly and the verification problem grows exponentially. And perhaps in many situations, the general applicability of the chip decreases as you specialize it more and more. But those are engineering trade-offs.
DITZEL In some sense designing a custom hardware chip for every specific use might be very well powered in some optimal sense. But if the chips are getting so complicated, it seems to me you'd want a more programmable chip.
You might want to use a chip for many different things. I'm thinking of some of the future video chips—for example, where the algorithm itself keeps changing often. Does that force us to do kind of these super megachips that are trying to cover many bases all at once? And can you really cover the power ranges people want from super-low power in your wristwatch all the way up to what your notebook computer would be?
DOBBERPUHL Hardwired logic is considerably more power efficient than programmable logic. We talked about high-performance processors being 10 times less efficient than low-power processors. Hardwired logic is probably on the order of 10 times more efficient from a power point of view than a good low-power processor. So there are serious advantages to hardwired logic in chips. The obvious disadvantage is that it's hardwired. Again, these are engineering trade-offs, and different situations demand different applications.
But it is generally true, I think, that programmability has been the direction that the industry has taken over time. Things that were originally hardwired eventually became programmable—because of the flexibility, the adaptability, the ability to fix bugs. There are a lot of advantages to programmability, but power is not one of them.
Evolution
DITZEL Do you think we're going to go through a period of evolution in the next several years? Or do you see some maybe unexplored technologies like a new circuit family or a new kind of transistor that's going to give us a big breakthrough? Or are we going to follow a Moore's-law curve?
DOBBERPUHL I think it's going to be pretty much evolutionary. There are improvements in the technology coming beyond the scaling that I think will be helpful. But they're not going to be orders-of-magnitude helpful. And we really have an orders-of-magnitude problem.
DITZEL There's a fairly famous chart I've seen that Pat Gelsinger at Intel did that showed chip power in PC processors from the original Intel 8086 chip up through the future. It unfortunately shows power drawn on a log scale. If we were to continue this trend, the heat density of these chips would be as hot as a nuclear reactor.
DOBBERPUHL That is correct.
DITZEL So what people say is, "Well, technology marches on, but obviously this can't continue." Where are we in terms of heading ourselves toward the big problem, and what are people going to do about it?
DOBBERPUHL I think we're there; we have a big problem. Power dissipation is limiting performance across the board, both on high-end devices, as well as on mobile devices. And we've got a lot of smart people working on it. There haven't been any super breakthroughs. But there have been evolutionary improvements.
DITZEL So you don't think it's practical for people to be building one-centimeter-square, one-kilowatt chips that go into consumer electronics devices?
DOBBERPUHL No, I do not. I don't remember the exact number, but on the order of a two-centimeter-square chip, you can't mechanically extract more than about a 100 watts without the temperature going up way too high.
So we're very much constrained in terms of how much total power an individual chip can dissipate per square centimeter on the high end. And on the low end we're constrained by thermals and batteries.
DITZEL So, Dan, a lot of the issues with power for the past 10 years have been worked on sometimes by what I'll call the circuit engineers, who have been trying to run at lower voltages and just take advantage of the natural scaling of semiconductor processes. Do logic designers, architects, and software programmers have anything to contribute in the future?
DOBBERPUHL Most definitely. We've developed lots of tools to do performance analysis for software development—and to understand the hot spots from a performance point of view in code and make improvements to tune code, to improve performance, or to reduce memory footprint, etc.
I think it's appropriate at this point to think about tools that would allow software programmers to analyze and optimize code for power dissipation. So far, as you say, most of the power conservation work has been done by the hardware engineers.
Chip designers have put a lot of hooks into silicon, many of which really haven't been fully exploited. Software really has the big context of what's going on in the system; the hardware has a very small understanding of what's going on. So the software should be able to do the best job of power management. But the hardware has to have the hooks to allow it to do it.
DITZEL Among the chips that are starting to take a lot more power these days are the graphics chips. In fact, they're taking as much or more power than the CPU chips are taking. Is there anything fundamentally different between a graphics chip and a microprocessor in terms of making it go toward low power in the future?
DOBBERPUHL I think it's also true that graphics chips have started to become more programmable. That probably exacerbates the power-dissipation problem. So I think that they really are facing the same problem that the microprocessor guys are in terms of managing performance and power.
DITZEL What do you expect your handheld device to do for you five years from now that your current device doesn't do? Thinking not so much in terms of technology, but if you could imagine a personal handheld device, what do you think we'll be able to do in the future that we can't do today?
DOBBERPUHL I think that, for sure, there's a path toward convergence of voice, video, and data. And we all want to have it with us all the time, and it's definitely possible and feasible. So I think with good engineering we'll have handheld devices that allow us to communicate in those three dimensions with great efficiency.
DITZEL In terms of technology that might save us, in the last few years we've heard a lot about something called silicon on insulator, a variation of standard CMOS. Is that going to replace standard CMOS technology in the future?
DOBBERPUHL Well, the proponents would say that it will, and the opponents will say that it won't, and only time will tell. The issue I think it struggles with is that it has an advantage over standard silicon in terms of performance and power of about 25 to 30 percent—which is about what you gain from one generation of silicon technology. It is a more complex technology, and it is more expensive. Because it's not in widespread usage, it's not at the same level of development as standard silicon at any point in time. That lag can wipe out its advantage. So it has been a struggle for it to go mainstream. Certainly there are those who predict that it will. But it's not there yet.
DITZEL So we've seen, sometimes, that a mobile chip, like a mobile Pentium chip, might cost more than a desktop chip—even though its megahertz seems to be lower. Why is a low-power chip more expensive sometimes than a higher-powered desktop?
DOBBERPUHL Sometimes it might be for marketing reasons. But there are certainly reasons why it might actually be more expensive to make.
One way to build a lower-power chip is to take one that's at the high end of the speed distribution and reduce its power-supply voltage to get a reasonable clock rate and low power. In that case, you're taking the very best-performance chips and turning them into low-power chips, so that's one reason.
The other reason might be that it uses some process enhancement and may just be fundamentally more expensive to build.
Final Comments
DITZEL Any final comments?
DOBBERPUHL I guess I'd like to turn the tables and ask you a few questions, Dave.
DITZEL Feel free.
DOBBERPUHL Transmeta has certainly made a mark in achieving a very unique approach to power minimization in a standard architecture, the X86 architecture. I'd be interested to hear what you think in terms of how much that architectural approach has contributed to your low-power success and how much of it is just straightforward power minimization through design?
DITZEL I think we get a reduction in the number of transistors. And for the part of the equation that's CV2f, reducing the transistors is a big component. So I would say at least half of our power advantages come from the simplicity of design and some other issues that come forward.
But I think that the other big part for Transmeta's chips is allowing other engineering teams—in this case, the software engineering teams—to contribute by putting in more sophisticated algorithms in how one might dynamically change the voltage, the megahertz, reading the temperature of the silicon, and using other on-chip parameters to have control of items—something you wouldn't attempt to do in hardware lest you did it wrong.
The fact that we can do some of these sophisticated control items in software lets us attempt a little bit more and attack the problem a little bit more vigorously. I think, as we've seen, reducing power is an issue. It's not that there's any one magic bullet, but it's doing 25 different things all right at the same time and letting each of the different groups—whether it's product engineering or working with the process or the logic designers—be able to contribute in a way where maybe there just hadn't been as much focus on it in previous years.
DOBBERPUHL Are you optimistic that you'll be able to continue making progress without hitting the wall?
DITZEL I think there's another good five to ten years of power reduction in place, where we'll take chips that to date have had to be substantially different architectures, like the StrongARM chips, because there were no low-power PC chips. I think in the future we'll be able to take standard PC architecture applications and make them just as low power as we have other so-called low-power chips today—to the point where we can have handheld devices that can be running full Microsoft Windows XP and where you wouldn't have to have a different operating system on your handheld device from your desktop device from your cellphone.
Then all these things could communicate and run applications. I don't think today about loading an application onto my cellphone. But I think in the future one can do that.
DOBBERPUHL Well, great, in five years let's look back and see how we did.
DITZEL OK, let's make a date.
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