ARM Delivers First Transaction-level SystemC Models For System-level Verification
CAMBRIDGE, UK – Nov. 19, 2003 – ARM [(LSE: ARM) (Nasdaq: ARMHY)], the industry’s leading provider of 16/32-bit embedded RISC processor solutions, today announced the availability of the first transaction-level SystemC models of ARM® cores targeted for system-level verification. The models leverage a joint donation to the Open SystemC Initiative (OSCI) by ARM, Cadence and STMicroelectronics which will accelerate the development of a standard in this area, enabling the rapid deployment of IP for system-level modeling.
With the increasing challenges inherent in nanometer design, the electronics industry is in need of new solutions to address system complexity issues quickly and efficiently. Leveraging the expertise of STMicroelectronics in system modeling design, ARM developed transaction-level models (TLM) of their popular ARM11™ family cores written in SystemC and validated these models with the Cadence® Incisive™ functional verification platform. The models utilize an application programming interface (API) developed in collaboration with STMicroelectronics and Cadence Design Systems that is optimized for early hardware-software verification of complex embedded systems.
“STMicroelectronics has worked with ARM and Cadence to continue the development of a SystemC transaction-level modeling (TLM) methodology for platform validation, and we have jointly donated the work to OSCI for inclusion in the SystemC standard,” said Frank Ghenassia, System & Architecture Technology Group’s manager at STMicroelectronics’ Central R&D. “We have proven the TLM methodology in our design flow for embedded software development and hardware verification, and are seeing excellent results in terms of the quality and rapid implementation in ARM core-based silicon.”
“This collaborative design chain effort between ARM, STMicroelectronics and Cadence demonstrates that the transaction-level SystemC modeling approach has the necessary performance for system-level verification.” said Mitch Weaver, vice president, System Functional Verification Group at Cadence. “Using this approach, STMicroelectronics has been able to verify embedded software six months prior to register transfer level (RTL) completion, significantly reducing their time-to-market.”
“ARM, Cadence and STMicroelectronics have worked as one company to develop and optimize transaction-level models that ensure a proven verification path for embedded systems developers using SystemC technology,” said Mike Muller, at ARM. “This collaboration has enabled us to support our advanced ARM11 family of processor cores with pre-verified SystemC models available for hardware and embedded software design that link tightly to the Incisive Platform.”
Availability
The ARM1136J-S™ System C processor models and the ARM1136JF-S™ SystemC processor models will be available in Q4 from ARM as part of the RealView® Model Library. Additional SystemC models of leading ARM processors and the complete ARM PrimeXsys™ platform will be available by the end of Q4 2003 from ARM. |
