Big Chips, Big Growth
By Ed Sperling, Electronic News -- 12/1/2003 11:07:00 AM
Wim Roelandts, president and CEO of Xilinx, sat down with Electronic News to talk about missed opportunities, the rising cost of developing ASICs and what will continue to drive the fabless model. What follows are excerpts of that interview.
Electronic News: Are you seeing any strength in end markets?
Roelandts: Spending in the enterprise is starting to move up. It is visible already in storage and networking infrastructure.
Electronic News: How about communications?
Roelandts. The communications industry is still weak, but there are good signs there will be increased spending on infrastructure. The consumer side is still good, but telecom is weak, and it will be weak for the rest of the year.
Electronic News: Are you seeing any signs of life at the regional Bell operating companies?
Roelandts: The RBOCs are starting to innovate. They have developed a standard for fiber to the home. They have to do that because cable is offering a very competitive story. The goal is to deliver video, voice and data. But they don’t plan to dig up streets yet. They will deploy it in new neighborhoods and developments.
Electronic News: From your vantage point, how’s your arch-competitor Altera doing?
Roelandts: They're a far away second.
Electronic News: But Altera gained some points over the past year at your expense, didn't it?
Roelandts: That's true. When we got to 130 nanometers and began working with copper and low k, low k was not working. We were delayed about three quarters. Altera did not go low k, so they were shipping product.
Electronic News: Have you solved that problem?
Roelandts: Yes. In addition, our strategy of dual fabs has turned out for us. Advanced technology is difficult to produce on 8-inch fabs. We have more production on 12 inches than any company as a percentage of revenue. We had 40 percent last year. In the September quarter, it was 50 percent.
Electronic News: What about the low k?
Roelandts: We got rid of low k. At some point it will be part of the mainstream, but 90 nanometer does not need low k. There is really not much of a gain. It's about 5 percent. We expected to get 10 [percent] to 15 percent.
Electronic News: You mentioned two fabs. Which ones are they?
Roelandts: IBM and UMC. With two fabs, you get risk reduction. We have 90 nanometers taped out on two fabs, and in this case we have working silicon. On 300 millimeter, we've been working with UMC for the past 1-1/2 years. IBM's 300 millimeter fab is still starting up.
Electronic News: Is that primarily for capacity?
Roelandts: Our philosophy of working with fabs is a little different. We want to build the biggest chips with the most advanced technology. The big opportunity is against ASICs. We started with a foundry partner ahead of time on this. We proposed an FPGA because it has a very regular structure. They develop the process, we develop the chip.
Electronic News: Will you split the market between IBM and UMC?
Roelandts: No. After the tapeout you have to pick your primary partner. The primary partner gets 70 percent, the secondary gets 30 percent.
Electronic News: How much of a role did IBM play in this?
Roelandts: The core was designed by IBM.
Electronic News: IBM is in a rather unusual role of being an IDM and a foundry and a systems vendor. Are there other changes afoot that we don't know about?
Roelandts: The semiconductor industry is an industry in transition. The IDMs are moving to a fabless model. I am also chairman of the [Fabless Semiconductor Association], and we have a Morgan Stanley study that says that by 2010, 35 percent of all silicon produced will be in foundries. That's more significant than it seems, because there are segments of the industry that will never go fabless-Intel, DRAM, opto and analog. That's 45 percent of the industry. That 35 percent is equal to 70 percent of the available market.
Electronic News: Because of the cost of developing chips at advanced process nodes?
Roelandts: Cost, the volume necessary to pay for it and the advanced technology itself. This is a massive change, and only a few companies have integrated these changes. According to iSuppli, last year there were 1,400 ASIC design starts. There were 14,000 FPGA starts in the bubble. Numerous companies have abandoned ASICs. There is massive change being driven by new developments in this market.
Electronic News: Speaking of new developments, how high are your R&D costs as a percentage of revenue?
Roelandts: About 18 percent of revenue. It was 13 percent.
Electronic News: Has that impacted the price of FPGAs?
Roelandts: Not significantly because we defray it over thousands of customers.
Electronic News: But aren't the FPGAs getting more complicated as well?
Roelandts: Yes. There are more gates and more complex systems.
Electronic News: The biggest problem faced by ASIC developers is design, both in terms of cost and time, and they're using some very expensive EDA tools. In the FPGA space, both Xilinx and Altera have been generating their own tools. Is that going to change?
Roelandts: The tools we focus on are place and route, and mappers. They're architecture-dependent. When you get into simulation and verification, we'll never do that. On the synthesis side we have our own synthesis tools, which are very different than synthesis for ASICs.
Electronic News: Are any EDA players working there?
Roelandts: Synplicity is the only company that historically did a good job. But there's a growing interest at Synopsys.
Electronic News: How many designers are using your tools?
Roelandts: We have 150,000 active users of our software.
Electronic News: How much of that is in Asia?
Roelandts: That's a very big subscriber base.
Electronic News: Has the notion of system on a chip from a merchant IP standpoint caught on?
Roelandts: It's growing. We have 500 soft cores available. Some are very sophisticated, such as PCI Express. We are the only one that supplies that core. Even today, no ASIC core is available. The problem is debugging. How do you debug 10 million to 20 million gates? We have an integrated logic analyzer, which collects data for a thousand clock ticks. It helps in debugging. Programmable logic is the only one that can do that, and it cuts design costs. |
