Intel, Ovonyx, OUM status report at IEDM next week.
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Session 10: Emerging Technologies — New Concept Memory
Tuesday, December 9, 9:00 a.m.
International Ballroom East
Yoshihiro Hayashi, NEC
9:00 a.m.
Introduction
9:05 a.m.
10.1 Current status of the phase change memory and its future, S. Lai and S. Hudgens, Intel Corporation, Santa Clara, CA and *Ovonyx Corporation, Santa Clara, CA
Chalcogenide based phase change memory is evaluated for future scalable memory. In this review, the physics and operation of the memory, current status as well as future scaling trend will be presented. The scaling projection shows that there is no physical limit to scaling down to 22 nm node.
Session 37: Solid State Devices — Advanced Memory Devices
Wednesday, December 10, 1:30 p.m.
Jefferson Room
Co-Chairs: Steve Chung, National Chiao Tung University
Mitsumasa Koyanagi, Tohoku University
1:30 p.m.
Introduction
1:35 p.m.
37.1 Writing Current Reduction for High-denisty Phase-change RAM, Y.N. Hwang, S.H. Lee, S.J. Ahn, S.Y. Lee, K.C. Ryoo, H.S. Hong, H.C. Koo, F. Yeung, J.H. Oh, H.J. Kim, W.C. Jeong, J.H. Park, H. Horii, Y.H. Ha, J.H. Yi, G.H. Koh, G.T. Jeong, H.S. Jeong and K. Kim, Samsung Electronics Co., Ltd., Kyunggi-Do, Korea
By developing a chalcogenide memory element that can be operated at low writing current, we have demonstrated the possibility of high-density PRAM. We have investigated the phase transition behaviors with varying contact size, cell size and thickness, nitrogen doping and cell structure. The finally obtained memory cell operates at 0.7mA.
2:00 p.m.
37.2 A Ge2Sb2Te5 Phase-Change Memory Cell Featuring a Tungsten Heater Electrode for Low-Power, Highly Stable, and Short-Read-Cycle Operations, N. Takaura, M. Terao, K. Kurotsuchi, T. Yamauchi*, O. Tonomura, Y. Hanaoka, R. Takemura, K. Osada, T. Kawahara and H. Matsuoka, Hitachi, Ltd., Tokyo, Japan and *Hitachi ULSI Systems Co., Ltd., Tokyo, Japan
This paper presents a Ge2Sb2Te5 memory cell with a tungsten electrode. The cell has the lowest reset current ever reported for a phase-change memory device. The factors responsible for re-amorphization, which increased the instability of crystallization are shown. The cell offers a read-time within 2 nsec, which allows 200MHz-chip operation
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