ISSCC 2004 -- OUM related
MEMORY FORUM
F2: Memory Circuit Design Forum: Non-Volatile Memories
Technology and Design
(Golden Gate Hall)
Organizer/Chair: Jagdish Pathak, Sub Micron Circuits Inc.,
San Jose, CA
Committee: Stefan Lai, Intel Corporation, Santa Clara, CA
Mark Bauer, Intel Corporation, Folsom, CA
Koji Sakui, Toshiba Corporation, Tokyo, Japan
Frankie Roohparvar, Micron Technology,
San Jose, CA
Thomas Jew, Motorola Inc. Austin, TX
Ali Sheikholeslami, University of Toronto,
Toronto, Canada
Takayuki Kawahara, Hitachi Ltd., Tokyo, Japan
Non-volatile memories are one of the oldest memories used in computer
applications. From the earliest core memories to modern day Flash, this
technology has seen significant innovations and surmounted many chal-lenges.
Non-volatile memories are surpassing the DRAM’s in density.
They are also becoming the technology drivers for some of the semicon-ductor
fabs – their application in memory cards, digital photography, cellu-lar
telephones, and program storage have surpassed the densities of any
other memory technology. In addition to high density, data retention of
many years (even after the power supply is turned off) makes non-volatile
memories very attractive for battery powered applications and portable
consumer devices.
The present day workhorse of non-volatile memories is the floating gate
structure. These structures utilize channel hot electron injection and
Fowler-Nordheim tunneling for program and erase mechanisms. There
have been many architectures proposed like; NOR, NAND, AND, DINOR
etc. These architectures tried solving the basic memory requirement of
higher density and faster speed. This floating gate structure is now show-ing
significant limitations: it requires high voltages and thick tunnel oxide
for program and erase, and the program and erase times are very slow. It
is becoming increasingly difficult to scale these structures to smaller
geometries. In addition, the process complexity of the floating gate struc-ture
also creates problems when embedding these memories in a logic
process.
There have been many circuit design and architectural innovations in last
decade to solve the scaling and speed issues of non-volatile memories.
Multi level cell designs, and page buffers for read / program are some of
them. New interest in SONOS structures with multi-bit designs is another
field of interest. Serial memory architectures with USB interface and a con-troller
are the backbone of memory sticks.
This advanced circuits forum will present several of the various technolo-gies,
architectures and design techniques used in modern day non-volatile
memories. The quality, reliability, and test issues of non-volatile memories
will be presented. The challenges of scaling, multi-level cell, and embed-ding
these technologies in SoC environment will be discussed. Many new
non-volatile technologies are emerging in the field and this forum will dis-cuss
the potential and challenges for these technologies.
18
SESSION 2 SALON 1-6
NON-VOLATILE MEMORY
Chair: Frankie Roohparvar, Micron Technology,
San Jose, CA
Associate Chair: Yukihito Oowaki, Toshiba, Yokahama, Japan
2.1 A 0.18 µm 3V 64Mb Non-Volatile Phase-Transition Random
Access Memory
1:30 PM
W. Cho
1
, B-H. Cho
1
, B-G. Choi
1
, H-R. Oh
1
, S-B. Kang
1
, K-S. Kim
1
,
K-H. Kim
1
, D-E. Kim
1
, C-K. Kwak
1
, H-G. Byun
1
, Y-N. Hwang
1
, S-J. Ahn
1
,
G-T. Jung
2
, H-S. Jung
2
, K. Kim
2
1
Samsung Electronics, Hwasung, Korea
2
Samsung Electronics, Yongin, Korea
A non-volatile 64Mb phase-transition RAM is developed by fully integrating
a chalcogenide alloy GST(Ge2Sb2Te5) into 0.18 µm CMOS technology. This
alloy is programmed by resistive heating. To optimize SET/RESET distri-bution,
a 512kb sub-core architecture, featuring meshed ground line, is
proposed. Random read access and write access for SET/RESET are
60ns, 120ns and 50ns, respectively, at 3.0V and 30
O
C.
53
E4: What Is The Next Embedded Non-Volatile Memory Technology?
(Salon 7)
Organizer: Young-Hyun Jun, Vice President, Memory Division,
Samsung Electronics, HwaSung, GyeongGi, Korea
Moderator: Thomas Jew, Manager, Semiconductor Products Sector,
Motorola Inc, Austin, Texas
This panel will discuss the design and technology trade-offs to be fared in selecting a cost-effective
embedded Non-Volatile technology. Current NVM technology requires high-volt-age
operation with slow write rates. To overcome these problems, technologies like FRAM,
MRAM, PCM (Phase Change Memory), and Nano-Crystal memories are potential con-tenders
for the next-generation NVM technology. The panelists will discuss which/when one
of these technologies will become the main-stream Non-Volatile solution for the next gen-eration.
Panelists:
Ki-Nam Kim, Vice President, Memory Division, Samsung
Electronics GiHeung, GyeongGi, Korea
Tomoyuki Ishii, Senior Researcher, System LSI
Department, Hitachi Central Research Lab., Tokyo, Japan
Sitaram Arkalgud, Director, MRAM Development
Alliance, Infineon Technologies, Hopewell Jct., NY
Saied Tehrani, Director, MRAM Technology
Development, Motorola, Chandler, AZ
Greg Atwood, Intel Fellow, Flash Memory Development, Intel,
Santa Clara, CA
Tom Davenport, Vice President, FRAM Development
Ramtron Intl., Colorado Springs, CO
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