Sematech plans April meeting on 3-D interconnects
by Dave Lammers, EETimes
Silicon Strategies
02/12/2004, 12:46 PM ET
AUSTIN, Texas -- International Sematech will sponsor a symposium on 3-D interconnects April 13-15 in Burlingame, California.
A follow-on industry conference April 14-15 also will consider 3-D integration and packaging technologies. The conference will be co-hosted by RTI International (Research Triangle Park, N.C.)
Traditional device scaling is driving on-chip interconnects to their physical limits. 3-D interconnects may produce similar performance and densities, enabling memory, logic, and optoelectronics devices to be interconnected in the vertical dimension.
The Sematech symposium on 3-D technology, modeling and process will feature presentations by James Lu and Dhivya Krishna of the Renssalear Polytechnic Institute, Krishna Saraswat of Stanford University, Jon Candeleria of Motorola Inc., Paul Lindner of the EV Group, and Rafael Reif of MIT.
"ISMT's strategic roadmap shows 3-D interconnects as an enabling bridge technology that is intended to both enhance performance and functionality of IC systems," said Navjot Chhabra, director of interconnect at Sematech.
Further information on the industry conference is available at techventure.rti.org, or from Matt Mecray, 207-829-6084 or mmecray@rti.org. More data on the ISMT-sponsored technical symposium can be obtained from Josh Wolf at 512-356-7872 or josh.wolf@sematech.org. |
