SI
SI
discoversearch

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor.  We ask that you disable ad blocking while on Silicon Investor in the best interests of our community.  If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.
Technology Stocks : Advanced Micro Devices - Moderated (AMD)
AMD 259.65+2.3%3:59 PM EST

 Public ReplyPrvt ReplyMark as Last ReadFilePrevious 10Next 10PreviousNext  
To: combjelly who wrote (120081)4/26/2004 5:14:37 PM
From: THE WATSONYOUTHRead Replies (1) of 275872
 
To solve the problem, TSMC went back to its library and memory compiler vendors, Artisan Components Inc. and Virage Logic Corp., to ask them to create redundant vias in the SRAM cells.

I really can't imagine there being enough room for redundant vias in an aggressively designed SRAM cell. Since these via issues are somewhat predictive in terms of the locations/environments in which they are likely to occur, design rules specifying redundant vias have been around for some time. However, quite special and rare circumstances are generally required to possibly cause a failure. I have never know SRAM cells to be among those circumstances. The low k saga continues. Sounds like IBM tossed in the towel on SILK. About time.

THE WATSONYOUTH
Report TOU ViolationShare This Post
 Public ReplyPrvt ReplyMark as Last ReadFilePrevious 10Next 10PreviousNext