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Technology Stocks : Intel Corporation (INTC)

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To: Tenchusatsu who wrote (177960)	5/13/2004 6:02:42 PM
From: TigerPaw	Read Replies (1) of 186894

If every local access to the L2 cache has to go out onto the bus for cache coherency purposes,.... I believe that is the case (with current OS) if there is more than one CPU chip. The OS just doesn't know if memory is shared or not without checking each access. A lone dual-core chip could avoid this bottleneck, but as soon as you try to expand you hit this coherency check slowdown. then there is no need for the MESI cache protocol or for writeback caches in the first place. This question has been settled way back in the early-90s when WB caches were invented in the first place. The strategies to avoid this endless checking is rather limited. The OS uses processor affinity, which means that once a task runs on a certain CPU the OS gives preference to running on the same CPU after a stall so that the L2 cache is still associated with the same data. That way coherency may have to be checked, but the data doesn't always have to be swapped. Critical tasks can be locked to a specific CPU. Otherwise it just runs the task when it is ready on the CPU that is least busy at the time. The external bus issue was not much of an issue when all memory references went through an external northbridge anyway. It has a proportionally greater effect on performance now. The advantage AMD has for dual core is as much the on-board memory controller as the hypertransport. Actually AMD has a bottleneck of it's own when the memory accessed by one CPU chipset is physically attached to the memory controller on another CPU chipset. The OS doesn't do much to try and avoid that performance penalty either. TP

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