I still think they hope to pull this off.
Yes, their ultimate goal is their proprietary ISA, so that all competitors can be locked out of computing. They are working on putting an "Itanium mode" into one of their future x86 processors. It would actually convert the multiple "bundled" instructions of each wide IA64 instruction into multiple micro-ops -- the same as used by the x86 section of the microprocessor.
Chances are this "out-of-order" approach to IA64 will be capable of higher throughput than the more straightforward approach of Itanium. Faster than x86? Not for an equivalent amount of silicon, but Intel doesn't care. They have more silicon capacity than they know what to do with anyway.
If this approach is "successful", it would actually prove the utter failure of the EPIC architecture. All the work of the compiler and careful bundling of instructions would be thrown out the window when the x86 engine inside this behemoth processor starts executing the equivalent micro-ops in the order IT sees fit.
Despite being technically "successful," OOO IA64 would still be a total failure economically. Even if Intel had a chip that ran x86 as good as Prescott and it ran IA64 almost as fast as Itanium tomorrow, what incentive is there to convert any software to IA64?
Intel will NOT be successful in killing x86 because of two indisuputable FACTS:
1. there is nothing computationally limiting in the x86 ISA with AMD64 extensions.
2. for a given amount of silicon, x86 is more efficient
1a. There is no reason an x86 CPU can't have a 4-input floating point pipeline like Itanium, or 6, or 8. And actually, anything >4 would do an Itanium no good, unless it is redesigned to be an OOO processor, which, as I said, pretty much defeats the purpose of the explicit parallellism.
1b. AMD64 can ultimately address 56 bits of physical memory and any software written for AMD64 is compatible with this higher limit.
1c. There is nothing in either ISA that makes either one more scalable in terms of number of CPUs.
1d. Much vaunted and undefined "RAS features" and "MCA" have nothing to do with ISA.
Point 2 is absolutely true now if you compare Itanium 130 nm CPUs to Opteron CPUs. The only advantage Itanium has in performance is the 4-issue FPU. What's that, 30mm of silicon, at most? Given the same amount of silicon, an Opteron could have the 4-issue FPU and more cache, and would crush the Itanium on both integer and floating point.
As geometries get smaller, point 2 will become more and more true for one simple reason. EPIC was designed so that its bundle of instructions could all be executed in one clock cycle all the time. Well, OOO designs are approaching 4 operations per clock cycle and will eventually exceed it. At that point a "perfect" EPIC processor will be slower than the competition, even at the same clock speed.
The only solution, as I said, is basically to throw out EPIC and convert it to an OOO processor.
Hey, I know I'm preaching to the choir here, I just had to get this stuff out.
Petz |
