Rambus XDR: a DIFFerence in a DIMM
Intel Developer Forum Pictures of lily
By Charlie Demerjian: Friday 10 September 2004, 15:21
THE BOYS FROM RAMBUS were at it again this last week, showing off a bunch of things they were only talking about last IDF. The first one was a XDR DIMM, or RIMM, or XDIMM, or something, I am not really sure. Whatever the name, think XDR RAM chips on a DIMM like form factor.
The sticks don't look all that different from DDR2 with square flip-chip packages on a board. If you look closer though, you can see it is keyed differently, two nearly central notches rather than the single one slightly offset of the DDR DIMMs. Look even closer and you can see the contacts on the edge of the module are tiered, the ones on the ends are a bit longer and wider. Hmmm, something is different here.
Just kidding. Compared to a DDR DIMM, everything is different. They had two working boards, the first had a single XDR module and a spacer and the second had a pair of modules.
The XDR setup pulls data from the module from two directions at once. If there are two modules, the first has data pulled from it from the north, and the second from the south. If there is only one module, the signaling from the north comes into the same ram chip as the signal from the south.
The XDR chip is capable of working at variable widths so it simply services two requests at once. Plug the second module back in, and it goes back to a narrower config, and the second module picks up the slack.
This allows the XDR setup to have a staggeringly high level of bandwidth. XDR is 16 bits wide at a 3.2GHz signalling rate, so you have an aggregate bandwidth of 6.4GBps. That is enough to saturate the modern P4 bus. One thing I didn't mention though is that this is per chip, not per module. A module can have eight chips, or nine with ECC. 8 * 6.4 = 51.2, or about the bandwidth number that people are bandying about for the PS3.
The big thing Rambus has been pushing lately is a memory controller capable of doing DDR and all of its variants, along with XDR signaling. If you design a chip with this interface, you can start with cheaper DDR or GDDR, and come out with a higher performance part, or a second generation running XDR. They had a demo up of a controller running both a GDDR variant and XDR at the same time. The memory controller is under the blue heatsink and the GDDR chip to the left.
But what, pray tell, would you use to design this stuff? Well, RMBS has that covered also. CadenceFister and Rambus teamed up, with Rambus buying some of Cadence's assets, and Rambus becoming Cadence's serial cells of choice. This team up means Rambus gets access to Cadence's customers and lets it use the tools they are familiar with right out of the box. It is a big win for Rambus, and potentially a differentiator for Cadence.
On the fab side, Rambus has also been busy. The RaSer PHYs and other bits have been qualified on both TSMC and UMC processes at 180, 130 and 90nm. This allows Rambus to offer a pretty complete end to end solution from IP to tools to fabs. I just want to see a graphics card with this tech, those things could always use more memory bandwidth. Yoohoo, NVidia and ATI, are you there? |
