6F2
Micron on the advantages of stacking, part two
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Gary Cheng, Jack Lu and Stephen Taylor, DigiTimes.com, Taipei [Wednesday 15 September 2004]
Note: This is the second part of a report compiled from comments made by Mark Durcan, Micron¡¯s CTO and VP of R&D, during an interview with DigiTimes in the second week of May and supplemented by information given by him during the company¡¯s 2004 analyst conference in Hong Kong. The first part was featured yesterday.
No need for high-K dielectrics in trench structures at 90nm?
Because of the problems Durcan perceives with using high-K dielectrics in trench structures, and the fact that the trench manufacturers have already invested in 193nm lithography ¨C an investment that will not be recouped solely with 0.11-micron production ¨C he believes they will push to the next level as quickly as possible. This will not be easy, but, as long as the aspect ratio on the trench cells can be increased, the manufacturers should be able to put off introducing new materials for another node.
According to the International Technology Roadmap for Semiconductors (ITRS), DRAM will progress from 110nm to 90nm as opposed to logic going from 130nm to 90nm. DRAM typically takes half steps that are roughly 18% linear shrinks. For these shrinks, the trench manufacturers need to maintain cell surface area. If one ignores the impact of moving to texturing or high-K dielectrics, maintaining the surface area (2¦Ðrd) of a cylinder when its radius (r) is being reduced by roughly 18% requires the depth (d) to be increased by almost 22% (1/0.82).
Illustration 3: Retaining a trench¡¯s surface area from 110nm to 90nm. Visualization by DigiTimes, Sep 2004.
At each node, the aspect ratio gets worse by 43% (trench width is reduced by 18%, and trench depth needs to be increased by 22% to retain surface area, hence the width:depth ratio drops by 67% [0.82/1.22]). With the trench manufacturers only recently being seen to resolve the problems they had at 0.11-micron, the move to 90nm with the same dielectric looks a fair way off.
Is it easier to integrate a vertical access device in a trench or a stack storage node?
Proponents of trench technology often claim that it is easier to integrate a vertical device in a trench storage node than in a stack one. Durcan disagrees. Because stack technology allows the manufacturer to build up and over the access device, whereas in trench architecture the planar access device takes up space that cannot be used for capacitance in the trench, stack technology allows planar access device technology to be executed.
When scaling access devices, it is essential to retain sufficient capacitance to store the charge, while retaining the ability to read and write in and out of the capacitor in a reasonable time.
Durcan said, ¡°I believe it is a lot easier to build a high-performance planar device than a high-performance three-dimensional device because you¡¯re dealing with single-crystal silicon, improving the ability to scale the L and get the trans-conductance you need. If you can avoid going vertical, then that¡¯s an asset, and the stack guys have that.¡±
Eventually everyone will have to have some vertical component in the access devices, but this may happen later for stack architecture than for trench. Durcan claims that, if and when this happens, the stack architecture will gain an additional advantage over trench. For a trench architecture, the vertical access device has to be built within the trench, so the gate is internal to the channel. In a stack structure, on the other hand, the vertical access device can be created by building a surround gate. The gate modulating the channel wraps around the channel and gives you better gate control, resulting in a higher performance device.
Illustration 5: Surround (left) versus interior (right) gate. Visualization by DigiTimes, Sep 2004.
The myth that equipment makers limit trench development
With fewer players in the trench camp and only a 30% combined market share, there are often suggestions that trench development is hitting pitfalls because of a lack of support from the equipment vendors. Durcan was quick to dispel this myth, ¡°People often talk about this, and it¡¯s true that there are less players in the trench camp ¨C especially doing deep trench ¨C but I don¡¯t think this is a fundamental issue; the other points are more critical. The technological difficulties associated with trench technology are the issue, and less fundamental is whether there are people to work with you.¡±
The myth that equipment makers are focusing on development for future, and not mature, fabs
Micron remains focused on reducing costs through manufacturing efficiencies. Micron continues to implement shrinks, using smaller process geometries in mature, 8-inch fabs. Micron recently completed its 110nm process technology transition and is already manufacturing products on its 95nm process. The company is ramping production on the 300mm line at the Manassas, Virginia fabrication facility. Micron¡¯s strategy to implement new process shrinks and integrate 300mm throughout its fabs worldwide when it was most cost-effective for the company has been challenged because equipment vendors want to focus on development for new 12-inch fabs, which represent new equipment demand, rather than replacement or upgrade demand. This has not yet been a problem for Micron, although Durcan agrees that this could be more of an issue in the future.
There have been many reports of other vendors launching new processes at 12-inch fabs and encountering significant problems. These reports would tend to suggest that Micron¡¯s approach is more conservative and more predictable. Micron itself is also involved in a 300mm ramp and many processes scale well, but some need significant re-optimization in the transition from 200mm to 300mm, according to Durcan.
Micron advances on many fronts
According to Durcan, Micron tends to be an early adopter of advanced technology. For example, at 0.13-micron, Micron had already implemented tungsten wordlines, as opposed to tungsten silicide wordlines, and as the company moved to MIM (metal-insulator-metal) capacitors, it adopted low-resistance storage nodes and atomic layer deposition. As a result, investment has been spread over time, and not all of it has been specific to 6F2 development. For its 300mm production on a 0.11-micron process, Micron has implemented a copper back-end line at its fab in Manassas, Virginia.
Photolithography roadmap
Apart from laying out structures appropriately to maximize the benefits from the patterns that need to be printed, the key to photolithography is low-K1 processing, or the ability to operate with feature sizes well below the wavelength of light that is available.
Table2: K1 roadmap
Node (nm)
150
130
110
95
80
65
¦Ë (nm)
NA
248
0.7
0.42
0.37
0.31
0.27
0.8
0.48
0.42
0.35
0.31
0.26
193
0.75
0.58
0.51
0.43
0.37
0.31
0.25
0.85
0.66
0.57
0.48
0.42
0.35
0.29
0.93
0.72
0.63
0.53
0.46
0.39
0.31
Source: Micron Hong Kong 2004 Analyst Meeting, May 2004. Compiled by DigiTimes.
Notes: NA: numerical aperture, ¦Ë: wavelength, Node: process resolution.
K1 = ( Resolution ¡Á NA ) / ¦Ë.
The wavelength of light is determined by the type of laser used by the scanner ¨C the mainstream 248nm and the newer 193nm nodes are both shown in Table 2 above. The numerical aperture of the lens indicates how much the lens bends the light. The lens complexity, size and cost all increase as the numerical aperture rises. Typically, higher numerical aperture lenses become available later, so time is implicitly shown in the table, from top left down to bottom right. Better resolutions can be generated by moving to shorter wavelengths, increasing the numerical aperture of the lens, or by operating at smaller K1 proportionality constant factors.
As time goes on, the available numerical apertures for a particular wavelength of light increase ¨C this is shown on the left of the table. The top row shows the progression of nodes that DRAM manufacturers are working to. It is clear to see that at different nodes, manufacturers have several options.
Micron¡¯s roadmap is shown by the black squares with white type. The gray boxes with white type are considered uncompetitive positions by Durcan because the required steppers are available so late that production will be late to market. The other squares are feasible options. As the numbers go to the right of these boxes, the physical resolution limits of the wavelength of the light are reached ¨C the physics allows 0.25¦Ë, which is a K1 factor of 0.25 with an NA of 1, which is the best you can do in air.
Micron¡¯s roadmap is historically unique in that the company has driven its 0.15-micron and 0.13-micron processes to lower K factors than the competition. The company has taken 248nm down to its 0.11-micron process and just recently to its 95nm process. Many of the competition have adopted 193nm steppers just to reach a 95nm process. Micron sees its experience as a significant advantage because it allows the company to: a) make the transitions later ¨C when the equipment, resists and materials are more mature; b) defer the capital expense, which is significant for these transitions; and c) get two nodes out of each stepper.
Since Micron¡¯s roadmap is an anomaly, the implications for stepper manufacturers are limited, but, as the competition has not built up its ability to operate at low-K1 factors, Micron predicts that they will not be able to wait for high NA steppers and will have to reinvest later, which is good news for the equipment makers.
Table 3: Factors helping Micron operate at low-K1 factors
Process area
Developments
Exposure Tool
Wavelength and NA
Custom Illumination
Dual Reticles
Immersion
Mask
Attenuated PSM
OPC and iterative design
Mask/Source Optimization
Chromeless or Hardshifted PSM
Resist/Process
Reflection Control
Thin resist
Hardmask
Chemical or thermal shrink
Source: Micron Hong Kong 2004 Analyst Meeting, May 2004. Compiled by DigiTimes.
Going beyond 65nm, there¡¯s no technology yet available that is capable of making this migration. Micron plans to achieve 65nm by moving to a 0.31 K1 factor at the 193nm node. Durcan believes the competition will need to develop this capability because there is no viable 157nm node available, and immersion lithography, which is the future direction of the industry, may or may not be available by that time.
Capacitor developments
For the last two decades, almost all DRAM capacitors (prior to the 0.11-micron node) were utilizing oxide or silicon-nitride capacitors ¨C called SIS (silicon-insulator-silicon) capacitors. At 0.11-micron, companies, including Micron, started to transition to higher-K dielectrics. At 0.11-micron, a couple of vendors transitioned to not only textured electrodes, but also high-K dielectrics and a metal top electrode ¨C an MIS (metal-insulator-silicon) capacitor. Going forward, Durcan sees the MIM (metal-insulator-metal) capacitor with a high-K dielectric as the key.
Micron MIM capacitor from the side (left) and in planar view (right).
Source: Micron Hong Kong 2004 Analyst Meeting, May 2004. Compiled by DigiTimes.
The MIM capacitor allows more charge per unit area, a reduction in texturing ¨C which enables use of both sides of the storage node container ¨C and a reduction in the overall height of structures that mitigates some of the pressure of aspect ratios as geometries get smaller and smaller. It also helps lower the parasitic resistance, which becomes a key issue as DRAMs continue to scale ¨C not only is capacitance sufficient to store the charge required to maintain the memory, but the charge must be written in and read out of the cell quickly enough for today¡¯s high-performance applications. According to Durcan, there are only three companies conducting this technology development. Two have it already; one of which is Micron. The third has yet to develop it.
Eight-layer laminate of roughly two atomic layers per laminate layer.
Source: Micron Hong Kong 2004 Analyst Meeting, May 2004. Compiled by DigiTimes.
One of the factors that Micron attributes to its success in building not just capacitors, but also other structures, is a technique called atomic layer deposition. Durcan said, ¡°If you¡¯re building a dielectric or storage node that¡¯s maybe 10 atomic layers deep, and you want to do it at a very high aspect ratio over some sort of retrograde structure, this is critical, and Micron is a very early adopter, not only in development, but also in manufacturing. Others may have this in a development sense, but they still have to learn how to implement it in a cost-effective way. We have already overcome that hurdle, but they still have to face it in the future.¡±
Interconnects not getting left behind
Historically interconnects have been more of a focus in the logic arena. However, as memory applications that require high bandwidth and low power become more important, the pressure is on to implement much higher performance interconnects.
Cross-section of 300mm 0.11-micron DRAM showing metal layer formed by damascene process, in which the mandril/form was formed first. The metal then went in and was CMP¡¯d off as opposed to being patterned and etched. Enlarged view shows tungsten gate.
Source: Micron Hong Kong 2004 Analyst Meeting, May 2004. Compiled by DigiTimes.
Micron believes its implementation of a dual-damascene copper process in its 300mm 110nm production is the first of its kind in the memory market. Apart from creating a higher-performance interconnect, Micron expects the damascene process to scale more effectively at larger wafer sizes, including 300mm. The company also sees the supplier community putting a lot more effort into the development of these processes, as opposed to scaling down aluminum line widths. Lastly, being closer to the logic manufacturers in terms of performance may bring additional pressure on the competition to retool.
Marc Durcan, Micron CTO and VP of R&D. Source: Micron, May 2004.
Note: The above article has been compiled from comments made by Mark Durcan, Micron¡¯s CTO and VP of R&D, in an interview with DigiTimes held in the second week of May of this year and supplemented by information given by him during the company¡¯s 2004 analyst conference in Hong Kong. |
