...at ISSCC, Intel presented two papers. One described a 512-Mbit NOR part that will move into production over the next year. The multilevel-cell (MLC) device supports concurrent 1.5-Mbyte/second programming throughput for data storage, and 166-MHz continuous-burst operation for code execution, said Intel flash engineer Mase Taub.
Another Intel presentation, by Rajesh Sundaram, described a novel architecture that puts an inductor charge pump into the same package as a 128-Mbit NOR memory array. The inductor charge pump simultaneously programs 16 to 32 bits, or the same number of bits that NAND devices program in parallel. The device's write time was improved to 3 Mbytes/s.
Ed Doller, chief technology officer of Intel's flash products group in Folsom, Calif., said the inductive charge pump is a demonstration technology that is not on Intel's product road map at this time. The 512-Mbit MLC part, however, is sampling now, starting with a 108-MHz version in 90-nanometer technology.
STMicroelectronics also presented a faster NOR part at ISSCC, describing a 256-Mbit MLC design with a 125-MHz read speed and a read-while-write capability. The device uses three reference voltages and one read voltage in a scheme that supports very low currents, said Corrado Villa, a wireless flash design manager at STMicroelectronics (Agrate Brianza, Italy).
Lower current, smaller decoders
"We no longer have to support both low and high currents. With this approach, we can use lower currents, and smaller decoders, with signals that are digital in nature rather than analog," Villa said.
While Intel used its 90-nm process for its 512-Mbit part, STMicroelectronics designed its 256-Mbit NOR flash with a 0.13-micron process. Both companies used a double-row programming architecture to achieve the higher speeds.
Intel's Doller said he will present data at the upcoming Intel Developer Forum, planned for early March, to rebut claims by the NAND camp that NOR is unsuited for the camera cell phone market. He said the 90-nm process and a 65-nm flash process that will move into volume production in late 2006 allow Intel to develop high-density MLC NOR parts that support both code and data storage needs. The 512-Mbit parts that the company is now sampling can be stacked in the same package to provide 1 Gbit for applications that require higher densities, he noted.
"We are sampling at 108 MHz today, will follow that with 133-MHz parts, and will be at the 166-MHz speed by next year," Doller said.
The NAND vendors squared off with 8-Gbit densities. A Toshiba-SanDisk part was made in a 70-nm CMOS technology, and has a much-improved write speed of 6 Mbytes/s, which Toshiba engineer Takhiko Hara said is competitive with single-level-cell flash memories. The designers put the control and I/O pads on the bottom of the chip. This reduces the pad area by half compared with previous generations, and it improves performance by shortening the data path between the bit-line control circuits and the pads, according to Hara.
Samsung Electronics engineer Dae-Seok Byeon said Samsung used a 63-nm CMOS process, and put the row decoders in the center and the peripheral circuitry at the bottom of the chip. The company doubled the write speed, or programming throughput, to 4.6 Mbytes/s from 2.3 Mbytes/s for the previous-generation Samsung part. The read throughput was improved from 16 Mbytes/s to 23 Mbytes/s by reducing the read cycle time from 50 nanoseconds to 30 ns, according to Samsung.
Hitachi Ltd. and Renesas Technology Corp. engineers presented a 4-Gbyte assisted-gate AND part with a read throughput of 22 Mbytes/s.
storagepipeline.com
QUESTION: Are these speeds of 104-166MHz (and hence double-row programming architecture) a problem for AMD?
Regards,
Rink
PS, CJ, I know the general picture too, but would rather much like to see the details CONFIRMED in a roadmap format at this very moment. Also a demo or announcement of anything functioning at 65nm (even only a SRAM block) would help a lot. |
