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Technology Stocks : Advanced Micro Devices - Moderated (AMD)

AMD 222.12

+0.5%

1:25 PM EST

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To: mas_ who wrote (156701)	4/17/2005 10:18:46 PM
From: Elmer Phud	Read Replies (1) of 275872

mas mas Bretzmann said the Hurricane chipset instead uses a mainframe technique known as snoop bus filtering, which means processors in multi-way setups do not have to inspect each other's caches in the event of a cache miss but can instead go straight to main memory, cutting latency by one-third. I believe HP has been doing the same thing with their cache accelerator. It basically maps the contents of the other 4-way FSB caches(in an 8-way system) and doesn't bother passing a transaction on to the other bus if it already knows the memory location isn't in use by the other bus. But I was under the impression that a memory transaction is issued to the memory controller and the other agents snoop it in real time. This is not a sequential process where the host agent first interrogates the other processors before going to the memory controller, it all happens simultaneously or concurrently. At least that has been my understanding.

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