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Technology Stocks : Intel Corporation (INTC)
INTC 36.15-0.6%Dec 24 12:59 PM EST
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To: Ali Chen who wrote (181283)5/19/2005 8:35:28 PM
From: Elmer Phud  Read Replies (1) of 186894
 
Mr Happiness

This effect means that each of your dies have fast/leaky spots and slow spots in different parts of the _same_ die, which means that each chip is likely both thermally limited and speed limited at the same time. Worse, this parametric intra-die variation can hit any functional unit, so the traditional speed-path post-silicon analysis does not work anymore, you can't determine and fix the speed path later because it is now non-deterministic. Because of intra-die variations, various test coupons and ring oscillators are no longer an indicator of the final chip speed. These are kind of "defects" that do not show in full in bare functionality testing at wafer level, but show out only under full-stress tests.

You are 10 years behind in your thinking. Go look up "transition fault" and "stuck at fault". They are both included, and more in modern wafer sort testing. The magazine you read must be very out of date.

Perhaps before you make too many more dumb statements you may try to organize your thoughts and present your point. Are you trying to make a case that Intel has to scrap a large number of those good die because they are later found to be too slow to sell due to intra-die parametric variations that can not be screened for at wafer sort? Do you mean to imply that Intel's sort yields are misleading? If so, misleading compared to what? Do you suggest that other semiconductor manufacturers are immune to the defect types mentioned above? If that's your claim then where's your data? If you have some other point then I'm afraid you're not doing a very good job of presenting it.
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