HP uses coding theory to make nano chip
(Nice to report good news here for a change)
Mark LaPedus
EE Times
(06/09/2005 12:30 AM EDT)
eetimes.com
SAN JOSE, Calif. — Hewlett-Packard Co. on Thursday (June 9) claims to have developed a new way to design future nano-electronic circuits using coding theory, an approach currently being used in certain math, cryptography and telecommunications applications.
HP Labs' coding technology enables what it calls a crossbar architecture, where a set of parallel nanoscale wires are laid atop another set of parallel wires at approximately a 90 degree angle.
This, in turn, sandwiches a layer of electrically switchable material in between. Where the material becomes trapped between the crossing wires, they can form a switch that represents a "1" or "0," the basic building blocks of computer code.
The company's first device based on the technology is a demultiplexer. It claims to have made working devices in the laboratory at the 30-nm half-pitch node. The International Technology Roadmap for Silicon (ITRS) predicts that 32-nm half-pitch chips could be in production in about seven to eight years.
Coding technology could result in "nearly perfect manufacturing yields," with equipment a thousand times less expensive than what might be required using future versions of current technologies, according to HP (Palo Alto, Calif.)
"We have invented a completely new way of designing an electronic interconnect for nano-scale circuits using coding theory, which is commonly used in today's digital cell phone systems and in deep-space probes," said Williams, HP Senior Fellow and director of quantum science research at HP Labs, in a statement.
"By using a cross-bar architecture and adding 50 percent more wires as an 'insurance policy,' we believe it will be possible to fabricate nano-electronic circuits with nearly perfect yields even though the probability of broken components will be high," he said. |
