Flash devices at 4bits/cell by 2006
Co-developers of the 4bit-per-transistor flash memory technology announced by Saifun last week expect to have commercial parts out early next year.
“The 4bit-per-cell products are in development now, and will be announced at the beginning of next year,” said a spokesman from Macronix, the Taiwanese flash memory specialist, which licenses the technology from Saifun.
Another co-developer, Spansion, said: “We have demonstrated the technology’s ability to store four bits-per-cell with a working proof-of-concept, which we refer to as QuadBit.”
Spansion did not give a time scale for its commercialisation of 4bits-per-transistor memory.
Roger Van Aken, from Macronix Europe, said: “It’s clearly at the edge of the state of the art which is an important milestone for us, being a company which has come from behind to have caught up with industry leaders like Spansion.”
Infineon, which licensed Saifun’s 2bit-per cell technology, said: “Our next technology node for flash memory will be 110nm and that will be for 2bits-per-cell. We are working in the direction of increasing the number of bits per cell, but cannot give technical details or a timeline.” [Infineon is clearly a full generation behind]
Meanwhile, manufacturers of the rival technology to metal nitride oxide semiconductor (MNOS)-based flash, 2bits-per-cell floating gate NAND flash, concede it will not be possible to add more bits-per-cell to their technology.
Sanjay Mehrotra, co-founder and CTO of floating gate NAND company SanDisk told Electronics Weekly recently: “If you add eight levels to multi-level cell NAND you give up speed, which would not make for a competitive product.”
Boaz Eitan, CEO of Saifun said: “There’s no way floating gate NAND can deliver 4bits per transistor. In floating gate you would need 16 levels.”
electronicsweekly.com
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