Where the silicon hits the board
Anthony Cataldo
(09/05/2005 9:00 AM EDT)
URL: eetimes.com
Once, chip designers could take packaging for granted. No more. With the introduction of low-k dielectric materials and silicon thermal densities that could fry an egg, packaging experts are joining design discussions at their earliest stages. Among them is 36-year-old Chris Scanlan, who a year ago was named vice president of package development for Amkor Technology after five years running the company's system-in-package business unit and developing packages for it. Anthony Cataldo, who covers semiconductors for EE Times, sat down with Scanlan to discuss, among other things, the evolution of stacking technology, package reliability concerns and the road to packages that are more environmentally friendly.
EE Times: Do chip designers today give enough thought to packaging?
Chris Scanlan: In the past, packaging was certainly an afterthought. But over the last five years that's changed considerably, to the point where packaging is an integral part of chip design. Device designers are starting to take packaging into consideration early in the design process, especially with the implementation of low-k dielectric wafer fab processes. It's become more important to consider packaging in the design phase such that we can consider interactions like stress-induced interactions that can cause reliability issues.
EET: What in low-k caused that change in mind-set?
Scanlan: In the initial stages, we saw failures in the low-k pad stack associated with the interaction of the assembly process and the package design that we hadn't seen in the past. This has really caused more interaction between wafer fab processes and packaging processes. In the future, looking toward 65-nanometer and 45-nm nodes and beyond, IDMs and wafer fab foundries are taking packaging into consideration and doing package engineering and process engineering in parallel with the design of pad stacks for low-k devices.
EET: How do you interact with the wafer foundries and how has the relationship evolved?
Scanlan: A growing number of our customers are fabless, relying on wafer foundries. Our relationship with the foundries has improved substantially over the last few years in terms of our cooperation. For example, we work with foundries in characterizing assembly processes that are compatible with their new low-k nodes and in general developing assembly processes and fab technologies in parallel. We share information regarding things like dicing of wafers, pad stack and corner designs, and we work together to develop application notes that we share with IC companies so that they can design their products for manufacturability — not only at the die-design level but so that those die designs will be compatible with the assembly processes in our factories.
EET: We spend a lot of time discussing the barriers to the next process technology node, such as 65 nm or 45 nm. Do parallel barriers exist in packaging?
Scanlan: As geometries on the IC shrink, the interconnect density in the package is increasing rapidly. The challenge for us is to keep pace with geometry decreases on the wafer side. It means driving smaller flip-chip pitches, driving much higher-density substrate technologies, driving much finer-pitch wire bonding. We are very focused on improving all these things in our tool set.
EET: Will you have to introduce new substrate materials as you move to these finer pitches?
Scanlan: Yes. We're putting a lot of effort now into trying to develop technologies that will not only increase our density substantially but also reduce our cost for the substrate. Currently, as we increase interconnect density, we're driving the cost up substantially. It's going to take a new way to manufacture substrates to reverse that trend.
EET: Stacked-chip technology seems to have come a long way in four or five years. What can you do now and where can you take it in the next five years?
Scanlan: The first application for high-volume stacked was really flash-plus-SRAM integration for cell phones. That was typically a two-die stack application. Over time, what we've seen is more integration of logic-plus-memory and logic-plus-logic die stacking and an increase in the number of devices in the stack to the point where we're now routinely integrating three or more devices in a stacked-die package. Since package height is important in 3-D packaging, we've had to deal with issues of how much you can thin the silicon wafer before you start seeing electrical performance shifts within the device, particularly for certain types of memory devices or analog ICs. Those challenges have been overcome for the most part. Going forward, the main limitations will continue to be the ability to integrate devices from multiple suppliers and being able to develop a business model that works when integrating devices from multiple suppliers.
EET: So do you think you can get better yield than stacking several die in a single package?
Scanlan: The yield we're concerned with is not necessarily the assembly yield. It's the final test yield. Assembly yield will be similar in both cases. Die stacking is a very high-yielding process. Where the yield loss comes in is final test yield, the same yield loss you might find in a single-chip package. You multiply all those yield numbers together in a four-die stacked package and, if you have one low-yielding device, all of a sudden you're throwing away many good devices along with each of these failures. The problem becomes much more complicated when those devices are owned by different companies. So now it's more difficult to complete the failure analysis to understand who's responsible for the failure and then to manage the risk of loss associated with that. That's one of the driving factors for package-on-package.
EET: I understand that it's getting more difficult to find materials with low thermal resistance to get the heat out of the package. Do you consider this a big challenge?
Scanlan: It's a huge challenge and it's one of the reasons why there's been a transition to flip chip in high-performance devices like graphics ICs. The biggest impact that we've seen is that it becomes all the more important to take thermal performance into consideration, even during the IC design phase. Amkor is getting involved with thermal analysis and thermal modeling all the way through the system level. During the IC design phase, we not only model the thermal performance of our customer's device in our package, but we take the next step to understand the performance of the combination of device and package technology in the end system.
EET: What kinds of packaging failures could crop up in the next few years?
Scanlan: We've been putting a lot of focus on two areas recently. One has to do with the transition to RoHS [Restriction of the Use of Certain Hazardous Substances] and green packaging. Initially, that drove a lot of development of materials that could withstand lead-free solder reflow temperatures of up to 260°C. We put in a lot of effort in the last four to five years to make sure our package families can support those reflow temperatures, so for the most part we've got that problem under control. The next issue becomes solder-joint reliability using lead-free solder balls. This particularly becomes an issue in portable applications where the packages have to withstand harsh drop-and-bend testing. The lead-free solder alloys used today are less reliable in drop-and-bend testing than eutectic tin-lead.
EET: Which types of packages are you focusing on in your R&D?
Scanlan: We've put a tremendous emphasis on developing flip-chip technologies for applications such as graphics, core logic, networking and computing, as well as wafer-level CSP technologies. We'll continue to do that. The other market segment we're heavily focused on is communications and consumer, and I'll combine them because the devices are essentially melding together and the packages are quite similar. These include things like package-on-package, increasing the number of die we can integrate into a stacked CSP and reducing the thickness and form factor of 3-D packages.
EET: Where are you today in meeting the RoHS requirements?
Scanlan: Over the last five years we've put a lot of energy into developing technologies that are environmentally friendly and that comply with new standards such as RoHS, largely driven by the European market. At this point, the majority of our packages are compatible with RoHS. Many are already compatible with green requirements as well. This has been beneficial to the industry as a whole because it's driven us to develop materials and processes that are much more reliable than those we had in production five years ago.
Chris Scanlan
Current position:
Vice president, package development, at Amkor Technology Inc.
Education: University of Wisconsin, BS, materials engineering, 1992; MS, materials engineering, 1994
Work experience: |
