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Ovshinsky’s Memories
by John Walko
Forty years after their invention, semiconductor companies are starting to get very serious about Stanford Ovshinky’s phase-change memories
Flash Has been the dominant process for non-volatile storage for two decades, and remains a healthy business, with versions used in many portable electronic products including mobile phones, memory cards and PDAs. However, even its strongest proponents agree it is likely to run out of steam as cell scaling becomes harder with smaller geometries. Between 1990 and 2000, the size of an individual flash cell was reduced by a factor of 30 to accommodate the needs of equipment makers. But there are physical limits to how much lower the size can go.
Recent announcements of advances with phase change materials and memory cell structures, from companies such as Philips, ST Microelectronics, Samsung, Intel, Elpida Memory, IBM and Infineon all suggest memories based on these materials – also referred to as chalcogenides – may be the ones to watch and beat.
Basics
Phase-change materials, which change their physical properties depending on whether they are in their amorphous or crystalline phase, are widely used in optical storage media such as DVD recordable and rewritable discs. In these discs it is the reflectivity of the material that changes, with a laser being used both to heat the material to the temperature required to effect a switch between the amorphous and crystalline phases, and to detect the resultant change in reflectivity.
In phase-change solid-state memory cells, an electric current replaces the laser radiation. The phase-change materials are deposited as an ultra-thin film on the surface of a silicon chip, and an electric current is used to effect the switch between phases and to detect the phase change via an electrical resistance measurement (see ‘I-V Characteristics’ panel). What makes these materials so promising for fast memories is that they can change between the different phases extremely quickly and allow an almost unlimited number of read/write operations.
Enthusiasm for phase-changes has waxed and waned over the years. The original invention was made in the 1960s by Stanford Ovshinsky at Energy Conversion Devices Inc. While studying an alloy of tellurium, arsenic, silicon and germanium Ovshinsky noted that pulses of electricity caused fast and reversible changes in the phases and electrical properties of the alloys. The materials and memory cells are sometimes referred to as ovonic memories, in recog-nition of Ovshinsky’s pioneering role.
The intellectual property associated with the use of the technology in semiconductors has now been licensed to Ovonyx Inc, which develops the underlying technology under the label Ovonic Unified Memory (OUM). Ovonyx has also licensed the technology to a number of companies including Intel, ST Micro-electronics and Elipha Memory. In addition, Ovonyx has a joint development programme with aerospace group BAe Systems to develop a version of the memory integrated with radiation-hardened CMOS. The companies say the phase-change material seems ideal for space applications in view of the promise of high density, high performance, low voltage, non-volatility and compatibility with standard CMOS processing.
“It is truly gratifying that such excellent companies are investing in and working on this. Though I can’t talk on behalf of our licensees, I feel the technology is now so well advanced that we can expect commercial applications in a short while,” Ovshinsky recently told the IEE Review.
“And once we have that, the focus will shift to the phase-change concept really coming into its own as the single cell structure capable of replacing not just flash, but dynamic access random memories (DRAM) and static memories (SRAM) as well, and thus live up to the promise of the unified memory. That would dramatically change the economics of the already huge semiconductor memories industry.”
“Specifically, as a flash replacement, it is fast write times and endurance that are all-important,” says Ovshinsky. “Typically, current flash technologies can support between 500,000 to one million cycles, while, in the laboratory, we have shown that chalcogenides alloys, we can reach 1013 or ten trillion write cycles.”
Ovshinsky believes the scalability of silicon processing represents a major advantage for phase-change memory, with projections showing that there is no physical limit to scaling down to the 22nm node – subject to overcoming some technical challenges, mostly related to process integration.
In Detail
The basic phase change material used in ovonic memory is an alloy of germanium, antimony and tellurium (GeSbTe) – the so-called ‘225’ or GST alloy. The phase conversion occurs as the material is heated and cooled. When melted it loses all crystalline structure, and rapid cooling below the glass-transition temperature locks the material in its amorphous state. This phase is stable near room temperature, but nucleation and crystallite growth rates increase as the melting temperature is approached.
To switch the memory element back to its conductive state, the material is heated to a temperature between the glass transition temperature and the melting temperature – resulting in rapid nucleation and crystal growth over a period of several nanoseconds. The crystal nucleation and growth rates depend on the exact composition of the chalcogenide alloy, and can vary by several magnitudes among different materials. Changes in the electrical properties of such alloys are even more dramatic, and electrical conductivity measurements between phases can differ by up to six orders of magnitude.
Creating an electronic memory from these materials requires an array of access transistors, with each transistor able to provide sufficient energy to melt the memory cell’s area of chalcogenide alloy. Clearly, a vital aspect of memory element design lies in ensuring effective thermal isolation between the memory element, the device metallisation and the substrate (an effective heat sink).
Recent work at Intel suggested the time required for switching to the amorphous state is typically less than 10ns to 30ns, and the thermal time constant of the cell structure is generally just a few nanoseconds.
“These materials are truly remarkable in their properties, and we still have to fully understand the underlying physics of how they manage such blindingly fast structural rearrangement of atoms,” says Professor Matthias Wuttig, group leader of a material research team at RWTH, Aachen, Germany.
Wuttig says his team has received strong support from European Union funded research initiatives to work on better understanding of these chalcogenides, along with backing from one of the major European semiconductor manufacturers.
He maintains that the key to future success is “to understand how small the devices can be made, and to ascertain the optimal switching power for the best type of phase transition.” Current work at the RWTH suggests switching can be brought down to less than 10ns in some GST-based alloys, and switching times as low as 1ns are within reach.
Giulio Casagrande, R&D director for memory products at ST Microelectronics, cautions: “While research has shown that memories using phase change materials can have significantly better read/write cycles compared with current generation flash, say 1010, realistically, and at least for the short to medium term, semiconductor companies like us are targeting an order of magnitude better.”
ST has a pre-competitive phase-change memory research programme with Intel, which, according to Casagrande, is concentrating on developing larger arrays and techniques for cost-effective production. “It is fair to imagine the shift to any volume production with phase-change memory will not happen for 10 years,” says Casagrade. “We have to develop generations of products, get some key customers on board, and sort out some vital six-sigma manufacturing and integration challenges.”
ST and Intel have already demonstrated a trench cell structure can be integrated into the mainstream chip manufacturing process, and have shown working phase-change memory memories that can be built with a 0.18µm CMOS process – an 8Mbit device in the case of ST.
Samsung has developed a ‘differential’ phase-change memory architecture that is said to increase reliability by representing each bit as a combination of one crystalline and one amorphous cell – demonstrating a 64Mbit device fabricated in a 0.18µm CMOS process.
In May, IBM, Infineon, and Taiwanese memories specialist Macronix said they would join forces to study and develop materials, structures and test chips based on phase change technology.
A New Twist
A few months earlier Philips revealed details of a phase-change memory cell made from doped antimony telluride that it says has a significantly lower threshold voltage than the OUM concept, promising improved scaling with future IC manufac-turing processes.
In this ‘line cell’ memory, switching between the amorphous and crystalline states occurs at an electric field strength of around 14V per micron. Thus, for a 50nm long strip of phase change material, the required voltage would be just 0.7V, which, according to Philips, provides an excellent match with the supply voltage for the next generation of silicon chips.
The thin strips of phase-change material are terminated by larger pads, also of phase-change material. These plugs are positioned directly over existing contact plugs, making the line cell memory much easier to integrate into existing CMOS processes. In addition, the phase change element in the line cell is surrounded by relatively low thermal conductivity silicon dioxide, avoiding interface reactions and providing an extra degree of freedom in the choice of electrode material. In early prototypes, the phase changes occurred at about 30ns intervals.
“Work is under way on the integration of these cells with CMOS transistors, and we are doing this in conjunction with researchers at IMEC in Belgium,” said Karen Attenborough at Philips Research.
She suggests the Philips line concept leads to significantly lower power dissipation than other approaches, lower voltages for shorter lines and thus shorter programming times (less than 50ns).
Industry Consensus
Any talk of the imminent demise of flash would be premature, and there is general agreement that recent advance in the flash process may well prolong its prospects. Exactly which variant of phase-change memory will prove the eventual replacement remains uncertain, and there are healthy and competitive exchanges between the prop-onents of the various materials employed and cell concepts deployed. But all the players are agreed that phase change memories will emerge from the current research phase as strong contenders to replace flash when the latter’s time is up.
I-V Characteristics
Three bias current levels control the opera-tion of the phase-change memory cell. To drive the phase-change material into the high-resistance amorphous state (RESET operation), the temperature must be increased above melting point, followed by cooling to prevent crystallisation and to ensure stabilisation in the disordered amorphous state (high-current opera-tion). The SET operation corresponds to the transition from the amorphous to the crystalline state. The material is heated to a temperature high enough to promote crystallisation, while remaining below melting point (intermediate-current operation). In the READ operation the current is kept low, avoiding thermal disturbances that could result in a possible change of state for the phase-change material. |
