SI
SI
discoversearch

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor.  We ask that you disable ad blocking while on Silicon Investor in the best interests of our community.  If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.
Politics : Formerly About Applied Materials
AMAT 318.63-3.0%Feb 3 3:59 PM EST

 Public ReplyPrvt ReplyMark as Last ReadFilePrevious 10Next 10PreviousNext  
To: Big Bucks who wrote (8072)9/21/1997 8:48:00 PM
From: olduvai5   of 70976
 
I'm new to this thread and have been intrigued by the current discussion re: efficiency of scale (300mm wafer size) vs. high levels of integration (possible decrease in chip demand). One factor not discussed yet, which I believe will be the dominant factor soon, is the spiraling costs associated with tooling up. Projections of fab costs I have seen for 300mm lines will be on the order of 3-5B within the 4 year time frame. Given that the obsolescence cycle requires retooling at 3-5 year intervals, the capital costs associated with these lines will have to be covered in the price received per chip. I think this will prevent the kind of collapse in CPU and VLSI prices we have seen in the memory market. If I'm wrong, then only the 4 or 5 biggest chip manufacturers will survive.
There was an interesting article in a recent Business Week about SGS Thomson's drive to move into the top 5 semi companies in order to ensure their survival in the coming Texas Death Match. It sure looks like Samsung, Hitachi and a couple of others are in a giant game of chicken!

olduvai5
Report TOU ViolationShare This Post
 Public ReplyPrvt ReplyMark as Last ReadFilePrevious 10Next 10PreviousNext