Joe, I think they are right on the QC timing, but wrong on the K8 vs. K8L thing.
From the Inq, last week:
Look at the first example, the "Deerhound" quad-core CPU based on the K8L core tune-up, which AMD is supposed to ship in volumes during the 3rd quarter of 2007. This Opteron-class server CPU has only 2MB of shared L3 cache according to my deep throat - less than the L2 cache on the current Woodcrest! if each core has its own 1MB L2, and there are four of them, what extra use is such a small common L3 for? Well, two answers - one is to remove the inter-core and cache coherency traffic from the crossbar and keep it within that L3 cache. And the other? Well, AMD might again rely on "exclusive" cache policy, not copying the data from L2 into L3 in this case, but keeping additional code and data there.
Further in mid-2008, using the same 65 nm process, AMD refreshes its line with new quad-core parts: "Cerberus" high-end Opteron MP, and "Wolfhound" Opteron DP. While Cerberus enjoys a larger (but still somehow weak) 6 MB L3 cache together with fast 2.4 GHz HyperTransport 3 (19.2 GB/s bandwidth per link, to match the built-in DDR3 memory controller speed), its DP cousin still sticks with paltry 2 MB L3 - and, hey, that is mid 2008 period!
theinquirer.net
So:
"Late 2007" = H207 = Q3 vol shipments for a first K8L QC "Deerhound".
Then the 2008 refresh with DDR3, etc. |
