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Technology Stocks : Advanced Micro Devices - Moderated (AMD)
AMD 242.05-1.7%12:15 PM EST
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To: combjelly who wrote (197871)5/19/2006 10:43:30 AM
From: MagratheaRead Replies (1) of 275872
 
I understood or agreed with nothing you wrote.

A. Being able to execute X86-32 and x86-64 implies to ability to execute some other instruction set, say, Alpha and/or Power along with these two. Some transistors would have to be spent to take care of architectural differences like the differences in the register sets, but it could be done.

B. Else, an Itanium approach can be taken where a whole, separate core is embedded.

C. But emulation is likely going to beat [Itanium's] approach as Intel learned.

D. Only AMD will spend more transistors to hide the backward incompatibilities, unlike the current Cell. This fits in with the rumored anti-HT that was being tossed around a couple of weeks ago.

A. x86-64 was designed to be compatible with x86-32. So it in no way implies Power+x86 is feasible.
B. Did Itanium embed an x86 ever?
C. I though the Itanium lesson is emulation of x86 was NOT the way to go.
D. Huh? I think we are 180 degrees apart.

My concept is that a separate non-x86 HT linked chip runs the different ISA code. The "subervising" x86 Opteron through a kind of virtualization makes the other chip think it is running on a native platform.

Opteron: "Let's see.... File00038.mix is an x86 wrapper around a CELL visualization executable... Here ya go buddy; have fun!

-Magrathea
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