ARM Unveils System Generator, RTL Design Flow
Staff Reporter -- 7/24/2006
Electronic News
reed-electronics.com
ARM today is debuting its RealView System Generator tool, a new member of the company’s RealView series of tools. The tool, which will be available in August, enables platform providers to rapidly generate, by themselves, instruction-accurate virtual prototypes that are scaleable, reusable and fast enough to interact with in real time, ARM said in a statement.
The tool will make its debut this week at the Design Automation Conference (DAC) in San Francisco.
The RealView System Generator keeps NRE costs under control and protects unique IP by dispensing with third-party consultancies, because, ARM said, it gives both hardware and software engineers the power to create and modify their own system models. The speed of the generated virtual prototypes is comparable to the speed of currently available mobile devices, making it possible to test application software as it will appear on the end device, months before hardware is available, the company said.
"For a highly differentiated consumer electronics product to succeed, electronics vendors need a way to generate application software, perform testing of hardware and application software integration and validate the end-user experience as early as possible," Bryn Parry, ARM's general manager of development said in a statement. "The RealView System Generator tool provides a target early in the design cycle that enables these tasks, and is easy to deploy."
The company said that silicon vendors, OS or software vendors or system OEMs working with SoC- or ASIC-based systems would be able to work on application software development in parallel with hardware development by using the System Generator tool, reducing integration time.
The first version of the System Generator includes fast processor core models for the ARM926EJ-S, ARM1136JF-S and ARM1176JZF-S processors, as well as for a number of ARM PrimeCell peripherals.
In a separate announcement, ARM also introduced today the joint development with Cadence Design Systems Inc. of the first automated RTL design and implementation flow for ARM's Corte-A8 processor. The ARM-certified flow is called "Cadence Encounter Express Flow for the Cortex-A8 Processor," and is touted by the companies to deliver 1,500 Dhrystone MIPS within a simple and synthesizable methodology, which allows SoC designers to quickly deploy high-performance, power-efficient processing in next-generation mobile, consumer and other applications, the companies said in a statement.
The Cortex-A8 processor features an advanced superscalar pipeline which can execute multiple instructions at the same time and deliver more than 2.0 DMIPS per MHz. For demanding consumer applications the Cortex-A8 synthesizable implementation will run at up to 750 MHz in generic 90-nanometer processes. For next-generation mobile devices the Cortex-A8 synthesizable processor implementation will run at over 500 MHz in 65nm low-power processes and occupy less than 4 mm2 of silicon.
The automated design flow, based on the Cadence Encounter digital IC design platform, was jointly developed by a team of ARM, Cadence Design Services, and Cadence Encounter R&D engineers over a year-long period.
The collaboration began in mid-2005 and culminated in a complete 90nm reference implementation. A number of RTL synthesis, placement, timing, and clock enhancements were developed specifically around the Cortex-A8 design, and are incorporated in the Encounter 2006.1 release, the companies said, which is shipping in production this month.
|
