Chris, In that case (same amount of metal layers) I have some doubt that 'fully scaling' currently used metal layers by itself will provide the 'big frequency boost' you claimed as a result. Maybe I have a different perspective: Can I ask you what you mean with 'big'?
In 130nm, Intel's metal 1 line pitch was 350nm. In 90nm, it went down to 220nm. That was really good, since 100% scaling would only have brought it to 242nm. So 90nm was actually more like a 82nm process if going by metal 1. Poly scaling was decent too, with almost 75% scaling.
Going from 90nm to 65nm, metal 1 only dropped to 210nm, which equals a 78nm process compared to 130nm. Poly is now like a 85nm process compared to 130nm.
Intel was quick getting to 65nm, the above explains why. Their tools are using the same 193nm wave length sources they used for 130nm.
What Intel has managed to do, to let its 65nm process earn its name, is scale the transistors down. That's why caches and other structures that are limited by transistor size, scales in size as expected - while large parts of the CPU core only sees very moderate size reductions, and part of that is only due to Intel adding metal layers (they're at 8 now).
Bottom line is that increased circuit performance almost entirely comes from improved transistor structures and materials.
What I've heard about the AMD 65nm process, is that they're using the latest equipment to scale the wire pitches significantly. As some have already noted, the transistors in AMD's 90nm process has been scaled down gradually over the process' lifetime. That's part of what AMD is touting as their flexible manufacturing - small changes every 3 months or so.
So, AMD's first 65nm transistors will look a lot like their last 90nm transistors. Differences being next generation strained gates and other smaller tweaks.
If AMD manages to scale the wires, we will see *big* improvements in frequencies.
So, what do I mean by *big* ?
Well, if the wires are scaled 100%, that means their area are halved in areas of the chip that are wire limited - like the core. That makes the wires "twice as fast" - well not entirely, since there's inductance too, and resistance changes in a nonlinear way in response to size reduction at nano scales.
Of course, wires isn't the only capacitive load a transistor has to overcome. The gates of the receiving transistors are capacitors too.
In some parts of the core, like execution units, gate capacitance is dominating, while in other parts, like bypass networks and result busses, wire capacitance is dominating.
This means a "dumb shrink" can't take full advantage of process improvements if wire and gate capacitances aren't improved equally - which they most likely aren't.
Anyway, the closest I can come to a clear answer, is that if the lowest metal layers are scaled, say, 70% and the transistors are improved as claimed by IBM/AMD, a "dumb shrink" could see a 40-50% boost.
A re-design targeted at the 65nm process could see as much as an additional 15-20%.
But again, this depends on the wire scaling - maybe it's less than 50%, or maybe it's 100% (I highly doubt it, but would be nice).
Of course, part of the frequency boost will be traded for lower power.
Another point, wire scaling is the tide that lifts all boats, so if AMD/IBM managed to pull it off, we should see the 65nm process hit the ground running - and not a replay of the 90nm introduction.
The AMD/IBM 65nm process has been a long time underway - hope it proves worth the wait. |
