So it is reasonable to expect a significant reduction in overall power consumption as a result of wire scaling; significant might be between say 15 and 35%
Things are connected. If voltage is reduced to 1.25V, power is reduced by 20%. The voltage reduction might be possible due to less need of drive strength, caused by less capacitive loading from wires.
So, do you attribute the 20% to lowered voltage and frequency, or to improved wiring ?
If voltage and frequency is raised again for some FX part, the improved wiring is now the cause of higher performance.
Anyway, if frequency is held the same as in 90nm, if wires are scaled significantly, if transistors are improved and voltage is dropped as much as possible - then power could drop maybe 60-70%.
But I don't see the relevance - AMD is in much greater need of performance, and that, together with the various markets needs, will dictate the tradeoff between power and performance that they chose.
On top of this power consumption will be reduced by ~15% as a result of improved SiGe based strain in the near future
Are you saying that 65nm will start out without improved strain ? I must've missed that info.
The QC K8 with the 128b FPU due summer '07 will be of a different design which might help too although the new FPU will probably consume more power than the old one
When being fully utilized, it will consume considerably more power than when doing scalar 64 bit operations. The difference between max power and normal power will thus likely be greater, as a percentage, compared to K8. |
