A deceiving story from a crook? Look below, UBS mentions competitors beating out Lattice...guess who? Note, the second and third stories about *Xilinx's* ISP products. Its well known that it is Xilinx who is aggresively introducing products to beat out Lattice and Altera...
And besides, Boucher is a crook...among other things, he hyped both Oak Technology and ESST immediately before major stock drops.
RESEARCH ALERT - Lattice (NASDAQ:LSCC) downgraded
Reuters, Friday, September 26, 1997 at 10:44
NEW YORK, Sept 26 (Reuter) - UBS Securities said on Friday
it reduced its rating on shares of Lattice Semiconductor Inc to
hold from buy, because of weakness in the programmable logic
device (PLD) market and valuation.
-- Analyst Charles Boucher said in a research note it might
be difficult for Lattice to avoid the weakness which has
permeated the PLD market.
-- "We also believe that Lattice's competitive advantage in
in-system programmability is diminishing, as competitors start
shipping ISP products," Boucher said.
...
***
Xilinx New Foundation Series Software Enables VHDL Design in Under Ten Minutes; Version 1.3 Now Shipping to Deliver Push-Button VHDL Design for the Industry's Highest Performance and Highest Density 3.3V FPGAs and ISP CPLDs
BusinessWire, Monday, September 22, 1997 at 08:06
SAN JOSE, Calif.--(BUSINESS WIRE)--Sept. 22, 1997--Xilinx, Inc.
(NASDAQ:XLNX) today announced delivery of the next version of its
Foundation Series software.
Xilinx Foundation Series version 1.3 software combines
easy-to-use VHDL design tools, advanced synthesis and optimization
technologies and push-button design flows that enable designers to
produce expert VHDL designs in minutes.
"The overwhelming acceptance of our Foundation Series solutions
confirms that Xilinx is truly bringing push-button VHDL design to the
desktop," said Rich Sevcik, Xilinx senior vice president software.
"With Foundation Series software, we are fueling the industry's
adoption of VHDL-based programmable logic design through complete
design solutions and the industry's highest clock rates."
Version 1.3 software also includes Xilinx new
architecture-specific optimization capabilities to easily balance
area and speed tradeoffs for optimum design results. These advanced
capabilities deliver a 20 percent improvement in design clock rates
with reductions in synthesis run-times of up to 50 percent compared
to previous versions.
...
***
Xilinx Announces Up to 41 Percent Price Reductions on ISP CPLDS; Price Reductions Places Xilinx as the Price Per Macrocell Leader
BusinessWire, Tuesday, September 02, 1997 at 08:16
SAN JOSE, Calif.--(BUSINESS WIRE)--Sept. 2, 1997--Reaffirming
its commitment to be the price leader for complex programmable logic
devices (CPLDs), Xilinx Inc.(NASDAQ:XLNX) today announced further
price reductions of up to 41 percent for selected XC9500 in-system
programming (ISP) CPLDs.
The new prices are effective immediately. This price reduction
is the third in nine months totaling up to 65 percent price reduction
on XC9500 devices. The company said it has made significant strides
in reducing manufacturing costs for the XC9500 devices with the
aggressive Flash process migration and manufacturing improvements to
allow Xilinx to pass further cost reductions on to the customers.
"Design wins for the XC9500 CPLDs are at an all-time high and have
doubled from the last quarter," |
