Formerly About Advanced Micro Devices Message Board

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Politics : Formerly About Advanced Micro Devices

Public Reply Prvt Reply Mark as Last Read File

Previous 10 Next 10 Previous Next

To: Elmer who wrote (23538)	9/26/1997 9:35:00 PM
From: Brian Hutcheson	of 1571927

Elmer , re. chipset knows nothing about the L2 cache... That does not make sense , since L2 cache has to be filled from DRAM before it can be accessed by CPU's cache controller and data transferred to L1 cache , THINK!! Brian

Report TOU Violation

Share This Post

Public Reply Prvt Reply Mark as Last Read File

Previous 10 Next 10 Previous Next