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Politics : Formerly About Advanced Micro Devices
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To: Brian Hutcheson who wrote (23545)9/26/1997 9:58:00 PM
From: Elmer   of 1571924
 
Brian, Yes the chipset responds to dram requests, but only if the memory location has not been cached. It just looks like another memory transaction to the chipset. Listen to me again,
the P6 chipset has no concept of cache. That's the beauty of the P6
generation of processors and why they are light years ahead of
the socket7 solutions.

I am getting a little tired of explaining all the misconceptions out there
about the P6 and it's associated chipsets and sockets.. It is amazing the level of ignorance on this thread. Why not study them first before
making assumptions? You just might learn something new. The P6
generation is a MAJOR break from the older x86 bus archeticure. It is
not based on bus cycles anymore but rather transactions. You need to
start thinking in a new way if you want to understand how it operates.

EP
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