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Politics : Formerly About Advanced Micro Devices
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To: Brian Hutcheson who wrote (23548)9/27/1997 12:04:00 AM
From: Elmer   of 1571780
 
Brian, I think the confusion lies in thinking that the L2 is between the processor and the dram. It is not. It is parallel to it. This is different for
the P6 archeticuture compared to the P5/K6. When the P6 processor
issues a memory access transaction, and that memory location is cached, the memory access transaction to the system is simply aborted when the cache signals that that location is cached. The
P6 specification provides signals called HIT# and HITM# to indicate
a cached memory location to both the chipset and other processors
in a multiprocessor system.

I'm sorry if I sounded condescending in my last post. This is not a
simple archeticure to explain. It is a radical departure from the x86 of the past. This is why the K6 and the 6x86 are at such a disadvantage.
The real advantages of the P6 archeticture only becomes apparent in
multi processor systems. This is why you will never see a K6 server.
It is simply obselete and every server manufacturer has known this for
nearly 2 years now. Intel based servers have been making enormous
inroads into the low to mid range markets and when Deschutes
appears they will challenge the high end, and do so effectively.

I hope my comments have shead some light. This is not a simple
archeticture to explain.

EP.
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