Elmer, few more of yours:
<When the P6 processor issues a memory access transaction, and that memory location is cached, the memory access transaction to the system is simply aborted>. When any CPU "issues a memory access transaction, and that memory location is cached", and the cacheline is not marked as "modified", THE MEMORY ACCESS TRANSACTION JUST NEVER HAPPENED! This is by definition of any reasonable cache controller!
FYI, "signals called HIT# and HITM#" have been a part of Socket7 signal from the day one.
<The real advantages of the P6 archeticture only becomes apparent in multi processor systems. This is why you will never see a K6 server.> For exactly the same reason, it is highly unlikely to see the P-II in majority of household computers! I do not need to remind you where the volume is...
If you wish to speak about servers, the P-II (with 512MB cacheable memory limits and 512k L2 cache) have no current chances to get into department servers. The P-II may be suitable only for hobbist's web servers and highly price-cautious small enterprizes, since the lack of performance has to be compensated by low price. Therefore, all "lucrative" advantages of the server market must be lost.
In summary, you are right, "This is not a simple archeticture to explain.". So please, do not try.
Ali. |
